Daniel Barros Jr.
According to our database1,
Daniel Barros Jr.
authored at least 10 papers
between 1998 and 2004.
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Bibliography
2004
Merging a DSP-Oriented Signal Integrity Technique and SW-Based Fault Handling Mechanisms to Ensure Reliable DSP Systems.
J. Electron. Test., 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
2003
J. Electron. Test., 2003
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
2002
Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
Summarizing a New Approach to Design Speech Recognition Systems: A Reliable Noise-Immune HW-SW Version.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001
Orienting Redundancy and HW/SW Codesign Techniques Towards Speech Recognition Systems.
Proceedings of the 2nd Latin American Test Workshop, 2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
1998
Reliability Verification of Fault-Tolerant Systems Design based on Mutation Analysis.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998