Daniel Bankman

Orcid: 0000-0002-0327-1813

According to our database1, Daniel Bankman authored at least 8 papers between 2015 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
An Always-On 3.8 $\mu$ J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019

RRAM-Based In-Memory Computing for Embedded Deep Neural Networks.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2018
An always-on 3.8μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Bit Error Tolerance of a CIFAR-10 Binarized Convolutional Neural Network Processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs.
Proceedings of the 55th Annual Design Automation Conference, 2018

BinarEye: An always-on energy-accuracy-scalable binary CNN processor with all memory on chip in 28nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2016
An 8-bit, 16 input, 3.2 pJ/op switched-capacitor dot product circuit in 28-nm FDSOI CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Mixed-signal circuits for embedded machine-learning applications.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015


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