Daniel A. Jiménez

Alaa R. Alameldeen

Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024

Practically Tackling Memory Bottlenecks of Graph-Processing Workloads.

[BibT_eX]

[DOI]

Alexandre Valentin Jamet

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering.

[BibT_eX]

[DOI]

Alexandre Valentin Jamet

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023

Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching.

[BibT_eX]

[DOI]

Elvira Teran

IEEE Comput. Archit. Lett., 2023

A Characterization of the Effects of Software Instruction Prefetching on an Aggressive Front-end.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

Rebasing Microarchitectural Research with Industry Traces.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Workload Characterization, 2023

2022

The Championship Simulator: Architectural Simulation for Education and Competition.

[BibT_eX]

[DOI]

CoRR, 2022

Dynamic Set Stealing to Improve Cache Performance.

[BibT_eX]

[DOI]

Brady Testa

Niranjan K. Soundararajan

Proceedings of the 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2022

Page Size Aware Cache Prefetching.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Thermometer: profile-guided btb replacement for data center applications.

[BibT_eX]

[DOI]

Shixin Song

Tanvir Ahmed Khan

Sara Mahdizadeh-Shahri

Akshitha Sriraman

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Composite Instruction Prefetching.

[BibT_eX]

[DOI]

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

SLAP-CC: Set-Level Adaptive Prefetching for Compressed Caches.

[BibT_eX]

[DOI]

Laith M. AlBarakat

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2021

Top Picks From the 2020 Computer Architecture Conferences.

[BibT_eX]

[DOI]

IEEE Micro, 2021

Morrigan: A Composite Instruction TLB Prefetcher.

[BibT_eX]

[DOI]

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Exploiting Page Table Locality for Agile TLB Prefetching.

[BibT_eX]

[DOI]

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020

PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron.

[BibT_eX]

[DOI]

Esmaeil Mohammadian Koruyeh

Gilles Pokam

Nael B. Abu-Ghazaleh

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

CHiRP: Control-Flow History Reuse Prediction.

[BibT_eX]

[DOI]

Gilles Pokam

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Support for Diverse Students.

[BibT_eX]

[DOI]

Proceedings of the KDD '20: The 26th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2020

Evolution of the Samsung Exynos CPU Microarchitecture.

[BibT_eX]

[DOI]

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Characterizing the impact of last-level cache replacement policies on big-data workloads.

[BibT_eX]

[DOI]

Alexandre Valentin Jamet

Lluc Alvarez

Marc Casas

Proceedings of the IEEE International Symposium on Workload Characterization, 2020

SB-Fetch: synchronization aware hardware prefetching for chip multiprocessors.

[BibT_eX]

[DOI]

Laith M. AlBarakat

Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing.

[BibT_eX]

[DOI]

CoRR, 2019

The impact of cache inclusion policies on cache management techniques.

[BibT_eX]

[DOI]

Luna Backes

Proceedings of the International Symposium on Memory Systems, 2019

Bit-level perceptron prediction for indirect branches.

[BibT_eX]

[DOI]

Tahsin Ahmad Khan

Proceedings of the 46th International Symposium on Computer Architecture, 2019

Perceptron-based prefetch filtering.

[BibT_eX]

[DOI]

Proceedings of the 46th International Symposium on Computer Architecture, 2019

2018

MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors.

[BibT_eX]

[DOI]

Laith M. AlBarakat

IEEE Comput. Archit. Lett., 2018

Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer.

[BibT_eX]

[DOI]

Sangam Jindal

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Flexible associativity for DRAM caches.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017

Multiperspective reuse prediction.

[BibT_eX]

[DOI]

Elvira Teran

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016

Sensible Energy Accounting with Abstract Metering for Multicore Systems.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2016

Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor.

[BibT_eX]

[DOI]

Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016

Perceptron learning for reuse prediction.

[BibT_eX]

[DOI]

Elvira Teran

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Minimal disturbance placement and promotion.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015

Adaptive GPU cache bypassing.

[BibT_eX]

[DOI]

Proceedings of the 8th Workshop on General Purpose Processing using GPUs, 2015

2014

Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Last-level cache deduplication.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Supercomputing, 2014

Adaptive placement and migration policy for an STT-RAM-based hybrid cache.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Improving cache performance using read-write partitioning.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013

WADE: Writeback-aware dynamic cache management for NVM-based main memory system.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2013

Temporal-based multilevel correlating inclusive cache replacement.

[BibT_eX]

[DOI]

Yingying Tian

ACM Trans. Archit. Code Optim., 2013

Insertion and promotion for tree-based PseudoLRU last-level caches.

[BibT_eX]

[DOI]

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Improving multi-core performance using mixed-cell cache architecture.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012

B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors.

[BibT_eX]

[DOI]

Reena Panda

IEEE Comput. Archit. Lett., 2012

Rank idle time prediction driven last-level cache writeback.

[BibT_eX]

[DOI]

Proceedings of the 2012 ACM SIGPLAN workshop on Memory Systems Performance and Correctness: held in conjunction with PLDI '12, 2012

Improving writeback efficiency with decoupled last-write prediction.

[BibT_eX]

[DOI]

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Decoupled dynamic cache segmentation.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011

Reducing network-on-chip energy consumption through spatial locality speculation.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2011, 2011

An optimized scaled neural branch predictor.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Exploiting Rank Idle Time for Scheduling Last-Level Cache Writeback.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Program Interferometry.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy.

[BibT_eX]

[DOI]

Yingying Tian

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Decoupled Cache Segmentation: Mutable Policy with Automated Bypass.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010

Sampling Dead Block Prediction for Last-Level Caches.

[BibT_eX]

[DOI]

Yingying Tian

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Insertion policy selection using Decision Tree Analysis.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Computer Design, 2010

Using dead blocks as a virtual victim cache.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009

Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization.

[BibT_eX]

[DOI]

Trans. High Perform. Embed. Archit. Compil., 2009

Generalizing neural branch prediction.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2009

Mixed-Signal Approximate Computation: A Neural Predictor Case Study.

[BibT_eX]

[DOI]

Renée St. Amant

Doug Burger

IEEE Micro, 2009

Composite Confidence Estimators for Enhanced Speculation Control.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing, 2009

2008

Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors.

[BibT_eX]

[DOI]

Gabriel H. Loh

Int. J. Parallel Program., 2008

Low-power, high-performance analog neural branch prediction.

[BibT_eX]

[DOI]

Renée St. Amant

Doug Burger

Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

A Two-Level Load/Store Queue Based on Execution Locality.

[BibT_eX]

[DOI]

Alexander V. Veidenbaum

Mateo Valero

Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007

Guest Editor's Introduction.

[BibT_eX]

J. Instr. Level Parallelism, 2007

An evaluation infrastructure for power and energy optimisations.

[BibT_eX]

[DOI]

Int. J. Embed. Syst., 2007

Efficient Program Power Behavior Characterization.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2007

A Flexible Heterogeneous Multi-Core Architecture.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006

Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors.

[BibT_eX]

[DOI]

Gabriel H. Loh

Proceedings of the 18th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), 2006

A decoupled KILO-instruction processor.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

2005

Improved latency and accuracy for neural branch prediction.

[BibT_eX]

[DOI]

ACM Trans. Comput. Syst., 2005

The Camino Compiler infrastructure.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2005

Idealized Piecewise Linear Branch Prediction.

[BibT_eX]

[DOI]

J. Instr. Level Parallelism, 2005

Chained In-Order/Out-of-Order DoubleCore Architecture.

[BibT_eX]

[DOI]

Proceedings of the 17th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2005), 2005

Code placement for improving dynamic branch prediction accuracy.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, 2005

Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor.

[BibT_eX]

[DOI]

Proceedings of the High-Performance Computing - 6th International Symposium, 2005

Piecewise Linear Branch Prediction.

[BibT_eX]

[DOI]

Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Toward an Evaluation Infrastructure for Power and Energy Optimizations.

[BibT_eX]

[DOI]

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004

Exploiting Procedure Level Locality to Reduce Instruction Cache Misses.

[BibT_eX]

[DOI]

Ravi V. Batchu

Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004

2003

Fast Path-Based Neural Branch Prediction.

[BibT_eX]

[DOI]

Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Reconsidering Complex Branch Predictors.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

2002

Neural methods for dynamic branch prediction.

[BibT_eX]

[DOI]

ACM Trans. Comput. Syst., 2002

2001

Dynamic Branch Prediction with Perceptrons.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

Boolean Formula-Based Branch Prediction for Future Technologies.

[BibT_eX]

[DOI]

Heather L. Hanson

Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001

2000

The impact of delay on the design of branch predictors.

[BibT_eX]

[DOI]

Stephen W. Keckler