Dan Alexandrescu
According to our database1,
Dan Alexandrescu
authored at least 49 papers
between 2000 and 2023.
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Bibliography
2023
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
2021
On Antagonism Between Side-Channel Security and Soft-Error Reliability in BNN Inference Engines.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects.
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020
Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact Models.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Microprocess. Microsystems, 2019
The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019
Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks.
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019
On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2019
2018
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018
2017
Microprocess. Microsystems, 2017
EDA support for functional safety - How static and dynamic failure analysis can improve productivity in the assessment of functional safety.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
2016
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
2015
Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
2014
New approaches for synthesis of redundant combinatorial logic for selective fault tolerance.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation.
Proceedings of the 19th IEEE European Test Symposium, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
J. Electron. Test., 2013
Pulse-length determination techniques in the rectangular single event transient fault model.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
2012
Test methodology of a new upset mechanism induced by protons in deep sub-micron devices.
Microelectron. Reliab., 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
2011
A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
2004
J. Electron. Test., 2004
2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
2000
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000