Damien Deleruyelle

Orcid: 0000-0003-2394-1359

According to our database¹, Damien Deleruyelle authored at least 15 papers between 2011 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2024

FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

1S1R Sub-Threshold Operation in Crossbar Arrays for Neural Networks Hardware Implementation.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on Mixed Design of Integrated Circuits and System, 2023

Investigation of resistance fluctuations in ReRAM: physical origin, temporal dependence and impact on memory reliability.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2023

Energy-efficient Computation-In-Memory Architecture using Emerging Technologies.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Microelectronics, 2023

2022

High temperature stability embedded ReRAM for 2x nm node and beyond.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Memory Workshop, 2022

1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Memory Workshop, 2022

2021

Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Reliability Physics Symposium, 2021

Ge-Se-Sb-N-based OTS scaling perspectives for high-density 1 S1R crossbar arrays.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Memory Workshop, 2021

2014

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories.

[BibT_eX]

[DOI]

Jacques-Olivier Klein

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.

[BibT_eX]

[DOI]

Jacques-Olivier Klein

J. Parallel Distributed Comput., 2014

2013

Synchronous full-adder based on complementary resistive switching memory cells.

[BibT_eX]

[DOI]

Yue Zhang

Erya Deng

Jacques-Olivier Klein

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Analytical study of complementary memristive synchronous logic gates.

[BibT_eX]

[DOI]

Jacques-Olivier Klein

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

2012

Non-Volatile Flip-Flop Based on Unipolar ReRAM for Power-Down Applications.

[BibT_eX]

[DOI]

J. Low Power Electron., 2012

Crossbar architecture based on 2R complementary resistive switching memory cell.

[BibT_eX]

[DOI]

Weisheng Zhao

Yue Zhang

Jacques-Olivier Klein

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

2011

Design challenges for prototypical and emerging memory concepts relying on resistance switching.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Damien Deleruyelle

Timeline

Legend:

Links

Online presence:

On csauthors.net:

Bibliography

Loading...