Damian Dalton

According to our database1, Damian Dalton authored at least 14 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2023
Machine Learning for Data Center Optimizations: Feature Selection Using Shapley Additive exPlanation (SHAP).
Future Internet, March, 2023

2011
Searching Extended IP-XACT Components for SoC Design Based on Requirements Similarity.
IEEE Syst. J., 2011

2010
An IP-XACT Library extended with verification information for functionality-based component selection.
Elektrotech. Informationstechnik, 2010

Automated simulation-based verification of power requirements for Systems-on-Chips.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2005
Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Parallel Simulation with a Generic Simulation Framework Featuring Loose Coupling.
Proceedings of the 34th International Conference on Parallel Processing Workshops (ICPP 2005 Workshops), 2005

2004
A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment.
Proceedings of the Integrated Circuit and System Design, 2004

A Generic Simulation Framework for Multiprocessor Architectures.
Proceedings of the Forum on specification and Design Languages, 2004

2003
APPLES: A Full Gate-Timing FPGA-Based Hardware Simulator.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

1999
A New Timing Mechanism Architecture for Discrete Logic Event Simulation.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

A special purpose hybrid SIMD processor for logic event simulation.
Proceedings of the Seventh Euromicro Workshop on Parallel and Distributed Processing. PDP'99, 1999

The Speedup Performance of an Associative Memory Based Logic Simulator.
Proceedings of the Parallel Computing Technologies, 1999

Analysis of an Associative Array Parallel Logic Simulator.
Proceedings of the 1999 International Conference on Parallel Processing Workshops, 1999

Avoiding Conventional Overheads in Parallel Logic Simulation: A New Architecture.
Proceedings of the High Performance Computing, 1999


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