Dale E. Hocevar
According to our database1,
Dale E. Hocevar
authored at least 19 papers
between 1982 and 2006.
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Bibliography
2006
A Reduced-Complexity, Scalable Implementation of Low Density Parity Check (LDPC) Decoder.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
2003
Proceedings of IEEE International Conference on Communications, 2003
Proceedings of the Global Telecommunications Conference, 2003
A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder.
Proceedings of the Global Telecommunications Conference, 2003
2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2001
Proceedings of the 54th IEEE Vehicular Technology Conference, 2001
Proceedings of the Global Telecommunications Conference, 2001
1998
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998
1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991
1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
1989
New implicit integration method for efficient latency exploitation in circuit simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989
1988
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988
1987
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987
1986
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986
1985
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985
1984
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984
1983
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983
1982