Daisuke Suzuki
Orcid: 0000-0002-2190-6528
According to our database1,
Daisuke Suzuki
authored at least 87 papers
between 2000 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
Design of a Nonvolatile-Neural-Network-Accelerator-Embedded Edge-IoT Device and Its Hardware Emulation.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
2022
Bypassing Isolated Execution on RISC-V using Side-Channel-Assisted Fault-Injection and Its Countermeasure.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
Evaluation of PPG Feature Values Toward Biometric Authentication Against Presentation Attacks.
IEEE Access, 2022
Attitude Control System Design of 3U CubeSat with Electrodynamic Tether for Post Mission Disposal Demonstration.
Proceedings of the IEEE/SICE International Symposium on System Integration, 2022
Proceedings of the IEEE/SICE International Symposium on System Integration, 2022
Orbital Demonstration of Gossamer Structure Shape Estimation using Time-of-Flight Camera System.
Proceedings of the IEEE/SICE International Symposium on System Integration, 2022
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022
Construction of a Quality Estimation Dataset for Automatic Evaluation of Japanese Grammatical Error Correction.
Proceedings of the Thirteenth Language Resources and Evaluation Conference, 2022
Proceedings of the Applied Cryptography and Network Security Workshops, 2022
2021
Timing Black-Box Attacks: Crafting Adversarial Examples through Timing Leaks against DNNs on Embedded Devices.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021
Low-cost distance-spoofing attack on FMCW radar and its feasibility study on countermeasure.
J. Cryptogr. Eng., 2021
IEICE Trans. Inf. Syst., 2021
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
Evaluation Framework for Performance Limitation of Autonomous Systems Under Sensor Attack.
Proceedings of the Computer Safety, Reliability, and Security, 2021
A Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once- Write Shifting.
Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021
Attack on PPG Biometrics: Presentation Attack by Stealth Recording and Waveform Estimation.
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
Towards Trained Model Confidentiality and Integrity Using Trusted Execution Environments.
Proceedings of the Applied Cryptography and Network Security Workshops, 2021
2020
IACR Cryptol. ePrint Arch., 2020
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
An Optimized Implementation of AES-GCM for FPGA Acceleration Using High-Level Synthesis.
Proceedings of the 9th IEEE Global Conference on Consumer Electronics, 2020
Photoplethysmographic Subject Identification by Considering Feature Values Derived from Heartbeat and Respiration.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020
Analysis of Driving Performance Data Considering the Characteristics of Railway Stations.
Proceedings of the Advances in Human Aspects of Transportation, 2020
2019
Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices.
Microelectron. J., 2019
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.
IEEE J. Solid State Circuits, 2019
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019
Analysis of Driving Performance Data to Evaluate Brake Manipulation by Railway Drivers.
Proceedings of the Advances in Human Factors of Transportation, 2019
2018
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018
Proceedings of the International Symposium on Micro-NanoMechatronics and Human Science, 2018
Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018
Proceedings of the 2018 on Asia Conference on Computer and Communications Security, 2018
2017
Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme.
IEICE Trans. Inf. Syst., 2017
Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Proc. IEEE, 2016
Asymmetric Leakage from Multiplier and Collision-Based Single-Shot Side-Channel Attack.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Proceedings of the IECON 2016, 2016
A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
Proceedings of the Digital Photography and Mobile Imaging XII, 2016
2015
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction.
IEEE J. Solid State Circuits, 2015
Faster Enumeration of All Maximal Cliques in Unit Disk Graphs Using Geometric Structure.
IEICE Trans. Inf. Syst., 2015
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.
Proceedings of the Symposium on VLSI Circuits, 2015
Development of the Multi-dimensional Robot Attitude Scale: Constructs of People's Attitudes Towards Domestic Robots.
Proceedings of the Social Robotics - 7th International Conference, 2015
Design of an MTJ-based nonvolatile lookup table circuit using an energy-efficient single-ended logic-in-memory structure.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
J. Cryptogr. Eng., 2014
Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure.
IEICE Electron. Express, 2014
2013
Using Pulse Laser Processing to Shape Cutting Edge of PcBN Tool for High-Precision Turning of Hardened Steel.
Int. J. Autom. Technol., 2013
Metastable Ordered Phase Formation in CoPt and Co<sub>3</sub>Pt Alloy Thin Films Epitaxially Grown on Single-Crystal Substrates.
IEICE Trans. Electron., 2013
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications.
IEICE Electron. Express, 2013
Proceedings of the IEEE International Symposium on Robot and Human Interactive Communication, 2013
A visibility improvement technique for fog images suitable for real-time application.
Proceedings of the Real-Time Image and Video Processing 2013, 2013
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the International Conference on Human-Robot Interaction, 2012
Circuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI.
Proceedings of the 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2012
2011
How to Decide Selection Functions for Power Analysis: From the Viewpoint of Hardware Architecture of Block Ciphers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
2010
Phototactic and Chemotactic Signal Transduction by Transmembrane Receptors and Transducers in Microorganisms.
Sensors, 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Increasing the Strength of Odors Produced by an Odor-Emitting Technology Using Odor Capsules.
IEICE Trans. Inf. Syst., 2010
Simultaneous detection of breath and alcohol using breath-alcohol sensor for prevention of drunk driving.
IEICE Electron. Express, 2010
Proceedings of the Cryptographic Hardware and Embedded Systems, 2010
2009
Olfaction Presentation System Using Odor Scanner and Odor-Emitting Apparatus Coupled with Chemical Capsules of Alginic Acid Polymer.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
A Study of Auditory Warning Signals for the Design Guidelines of Man-Machine Interfaces.
Proceedings of the Human Interface and the Management of Information. Information and Interaction, 2009
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009
2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Proceedings of the Cryptology and Network Security, 7th International Conference, 2008
2007
Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
IEICE Trans. Electron., 2007
Proceedings of the Cryptographic Hardware and Embedded Systems, 2007
2006
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006
2005
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005
2004
Random Switching Logic: A Countermeasure against DPA based on Transition Probability.
IACR Cryptol. ePrint Arch., 2004
2002
IEEE Trans. Biomed. Eng., 2002
A high-level synthesis method for simultaneous placement and scheduling considering data communication delay.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2000
Proceedings of the Intelligent Problem Solving, 2000