Mitigation of Accuracy Degradation in 3D Flash Memory Based Approximate Nearest Neighbor Search with Binary Tree Balanced Soft Clustering for Retrieval-Augmented AI.

[BibT_eX]

[DOI]

Shinichi Sasaki

Yuta Aiba

Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024

2023

SimplyRetrieve: A Private and Lightweight Retrieval-Centric Generative AI Tool.

[BibT_eX]

[DOI]

CoRR, 2023

Can a Frozen Pretrained Language Model be used for Zero-shot Neural Retrieval on Entity-centric Questions?

[BibT_eX]

[DOI]

CoRR, 2023

RaLLe: A Framework for Developing and Evaluating Retrieval-Augmented Large Language Models.

[BibT_eX]

[DOI]

Proceedings of the 2023 Conference on Empirical Methods in Natural Language Processing, 2023

2022

Revisiting a kNN-Based Image Classification System with High-Capacity Storage.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ECCV 2022, 2022

2021

Adaptive Quantization Method for CNN with Computational-Complexity-Aware Regularization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020

Weight Compression MAC Accelerator for Effective Inference of Deep Learning.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2020

2019

A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Post Training Weight Compression with Distribution-based Filter-wise Quantization Step.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019

2018

A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017

A Neuromorphic Chip Optimized for Deep Learning and CMOS Technology With Time-Domain Analog and Digital Mixed-Signal Processing.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

LogNet: Energy-efficient neural networks using logarithmic computation.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

2016

Convolutional Neural Networks using Logarithmic Data Representation.

[BibT_eX]

[DOI]

Daisuke Miyashita

Edward H. Lee

Boris Murmann

CoRR, 2016

Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

Mixed-signal circuits for embedded machine-learning applications.

[BibT_eX]

[DOI]

Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014

An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2014

3D-integrated, low-height, small module design techniques for 4.48GHz, 560MHz-bandwidth TransferJet™ transceiver.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Radio and Wireless Symposium, 2014

19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

A -70 dBm-Sensitivity 522 Mbps 0.19 nJ/bit-TX 0.43 nJ/bit-RX Transceiver for TransferJet<sup>TM</sup> SoC in 65 nm CMOS.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2013

A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A supply-noise-rejection technique in ADPLL with noise-cancelling current source.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC 2013, 2013

2012

A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2012

A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2012

2011

A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

2010

A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS.

[BibT_eX]

[DOI]