Daiki Hirabayashi

According to our database, Daiki Hirabayashi authored at least 7 papers between 2011 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

A CMOS PWM Transceiver Using Self-Referenced Edge Detection.

Kiichi Niitsu, Yusuke Osawa, Naohiro Harigai, Daiki Hirabayashi, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi

IEEE Trans. Very Large Scale Integr. Syst., 2015

2013

Multi-bit Sigma-Delta TDC Architecture with Improved Linearity.

Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Daiki Hirabayashi, Yuta Arakawa, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu, Yuji Yano, Tatsuhiro Gake, Takahiro J. Yamaguchi, Nobukazu Takai

J. Electron. Test., 2013

Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges.

Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

A clock jitter reduction circuit using gated phase blending between self-delayed clock edges.

Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Masato Sakurai, Osamu Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi

Proceedings of the Symposium on VLSI Circuits, 2012

A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS.

Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Multi-bit sigma-delta TDC architecture with self-calibration.

Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu, Yuta Arakawa, Daiki Hirabayashi, Yuji Yano, Tatsuhiro Gake, Nobukazu Takai, Takahiro J. Yamaguchi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements.

Masato Sakurai, Kiichi Niitsu, Naohiro Harigai, Daiki Hirabayashi, Daiki Oki, Takahiro J. Yamaguchi, Haruo Kobayashi

Proceedings of the International SoC Design Conference, 2011