Daijoon Hyun
Orcid: 0000-0002-0576-9666
According to our database1,
Daijoon Hyun
authored at least 25 papers
between 2015 and 2024.
Collaborative distances:
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Bibliography
2024
Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVs.
IEEE Trans. Very Large Scale Integr. Syst., May, 2024
Accurate Interpolation of Library Timing Parameters Through Recurrent Convolutional Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024
Fast IR-Drop Prediction of Analog Circuits Using Recurrent Synchronized GCN and Y-Net Model.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop Stacking.
ACM Trans. Design Autom. Electr. Syst., July, 2023
Integrated Power Distribution Network Synthesis for Mixed Macro Blocks and Standard Cells.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2021
Traitement du Signal, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Routability Optimization for Extreme Aspect Ratio Design Using Convolutional Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Proceedings of the International SoC Design Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
ACM Trans. Design Autom. Electr. Syst., 2019
ACM Trans. Design Autom. Electr. Syst., 2019
Selective Use of Stitch-Induced Via for V0 Mask Reduction: Standard Cell Design and Placement Optimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015