Daichi Fujiki

According to our database, Daichi Fujiki authored at least 19 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Restricted Random Pruning at Initialization for High Compression Range.

Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura

Trans. Mach. Learn. Res., 2024

Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket.

Hikari Otsuka, Daiki Chijiwa, Ángel López García-Arias, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Susumu Takeuchi, Masato Motomura

CoRR, 2024

OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration.

Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

HALO-CAT: A Hidden Network Processor with Activation-Localized CIM Architecture and Layer-Penetrative Tiling.

Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka

CoRR, 2023

MVC: Enabling Fully Coherent Multi-Data-Views through the Memory Hierarchy with Processing in Memory.

Daichi Fujiki

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Vector-Processing for Mobile Devices: Benchmark and Analysis.

Alireza Khadem, Daichi Fujiki, Nishil Talati, Scott A. Mahlke, Reetuparna Das

Proceedings of the IEEE International Symposium on Workload Characterization, 2023

2022

Multi-Layer In-Memory Processing.

Daichi Fujiki, Alireza Khadem, Scott A. Mahlke, Reetuparna Das

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2021

In-/Near-Memory Computing

Daichi Fujiki, Xiaowei Wang, Arun Subramaniyan, Reetuparna Das

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01772-8, 2021

A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array.

Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw

IEEE J. Solid State Circuits, 2021

2020

SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space.

Daichi Fujiki, Shunhao Wu, Nathan Ozog, Kush Goliya, David T. Blaauw, Satish Narayanasamy, Reetuparna Das

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

A 2.46M reads/s Genome Sequencing Accelerator using a 625 Processing-Element Array.

Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019

Near-memory data transformation for efficient sparse matrix multi-vector multiplication.

Daichi Fujiki, Niladrish Chatterjee, Donghyuk Lee, Mike O'Connor

Proceedings of the International Conference for High Performance Computing, 2019

Duality cache for data parallel acceleration.

Daichi Fujiki, Scott A. Mahlke, Reetuparna Das

Proceedings of the 46th International Symposium on Computer Architecture, 2019

2018

AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation.

Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

GenAx: A Genome Sequencing Accelerator.

Daichi Fujiki, Arun Subramaniyan, Tianjun Zhang, Yu Zeng, Reetuparna Das, David T. Blaauw, Satish Narayanasamy

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

In-Memory Data Parallel Processor.

Daichi Fujiki, Scott A. Mahlke, Reetuparna Das

Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017

High-Bandwidth Low-Latency Approximate Interconnection Networks.

Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

In-memory Data Flow Processor.

Daichi Fujiki, Scott A. Mahlke, Reetuparna Das

Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016

Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication.

Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano

Proceedings of the 24th Euromicro International Conference on Parallel, 2016