Dahun Choi
According to our database1,
Dahun Choi
authored at least 9 papers
between 2021 and 2024.
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Bibliography
2024
Mobile-X: Dedicated FPGA Implementation of the MobileNet Accelerator Optimizing Depthwise Separable Convolution.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2024
Survey of convolutional neural network accelerators on field-programmable gate array platforms: architectures and optimization techniques.
J. Real Time Image Process., May, 2024
HLQ: Hardware-Friendly Logarithmic Quantization Aware Training for Power-Efficient Low-Precision CNN Models.
IEEE Access, 2024
ARC: Adaptive Rounding and Clipping Considering Gradient Distribution for Deep Convolutional Neural Network Training.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Mixed Precision Quantization with Hardware-Friendly Activation Functions for Hybrid ViT Models.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
GDS: Gradient Distribution Scaling-based Gradient Quantization for Low-complexity and Hardware-friendly Training of Instance Segmentation Models.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
SRU-Q: Hardware-friendly Stochastic Rounding Unit-based Gradient Quantization for CNN Training.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Hardware-friendly Log-scale Quantization for CNNs with Activation Functions Containing Negative Values.
Proceedings of the 18th International SoC Design Conference, 2021