Daeyeal Lee
Orcid: 0000-0003-0778-0110
According to our database1,
Daeyeal Lee
authored at least 15 papers
between 2006 and 2022.
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Bibliography
2022
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2022
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing.
ACM Trans. Archit. Code Optim., 2022
Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform.
IEEE Access, 2022
2021
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT.
IEEE Trans. Very Large Scale Integr. Syst., 2021
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Embed. Syst. Lett., 2021
CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
2020
Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2006
Proceedings of the 15th Asian Test Symposium, 2006