Daewon Ha
According to our database1,
Daewon Ha
authored at least 9 papers
between 2003 and 2024.
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Bibliography
2024
Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate.
CoRR, 2024
Proceedings of the IEEE International Reliability Physics Symposium, 2024
Proceedings of the IEEE International Reliability Physics Symposium, 2024
Exploring Innovative IGZO-channel based DRAM Cell Architectures and Key Technologies for Sub-10nm Node.
Proceedings of the IEEE International Memory Workshop, 2024
Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation.
Proceedings of the IEEE International Memory Workshop, 2024
2023
Proceedings of the IEEE International Memory Workshop, 2023
2022
Prospective Innovation of DRAM, Flash, and Logic Technologies for Digital Transformation (DX) Era.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2003