Daewon Ha

According to our database1, Daewon Ha authored at least 14 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

2005
2010
2015
2020
0
5
10
1
1
9
1
1
1

Legend:

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In proceedings 
Article 
PhD thesis 
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Other 

Links

On csauthors.net:

Bibliography

2024
Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate.
CoRR, 2024

Highly manufacturable Self-Aigned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-dimensional Stacked FET at 48nm gate pitch.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Highly Robust All-Oxide Transistors with Ultrathin In2O3 as Channel and Thick In2O3 as Metal Gate Towards Vertical Logic and Memory.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Ge(110) GAA Nanosheet / Si(100) Tri-gate Nanosheet Monolithic CFETs Featuring Record-High Hole Mobility.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND Beyond 1K Layers: Experimental Demonstration and Modeling.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Low-Damage Processed and High-Pressure Annealed High-k Hafnium Zirconium Oxide Capacitors near Morphotropic Phase Boundary with Record-Low EOT of 2.4Å & high-k of 70 for DRAM Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024



Exploring Innovative IGZO-channel based DRAM Cell Architectures and Key Technologies for Sub-10nm Node.
Proceedings of the IEEE International Memory Workshop, 2024

Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation.
Proceedings of the IEEE International Memory Workshop, 2024

2023
Improvement of GIDL-assisted Erase by using Surrounded BL PAD Structure for VNAND.
Proceedings of the IEEE International Memory Workshop, 2023

2022
Prospective Innovation of DRAM, Flash, and Logic Technologies for Digital Transformation (DX) Era.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2017
12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2003
Extremely scaled silicon nano-CMOS devices.
Proc. IEEE, 2003


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