Daesun Oh

According to our database, Daesun Oh authored at least 10 papers between 2006 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

Low-Complexity Switch Network for Reconfigurable LDPC Decoders.

Daesun Oh, Keshab K. Parhi

IEEE Trans. Very Large Scale Integr. Syst., 2010

Min-Sum Decoder Architectures With Reduced Word Length for LDPC Codes.

Daesun Oh, Keshab K. Parhi

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009

Low Complexity Decoder Architecture for Low-Density Parity-Check Codes.

Daesun Oh, Keshab K. Parhi

J. Signal Process. Syst., 2009

2008

Area efficient controller design of barrel shifters for reconfigurable LDPC decoders.

Daesun Oh, Keshab K. Parhi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Nonuniformly quantized min-sum decoder architecture for low-density parity-check codes.

Daesun Oh, Keshab K. Parhi

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Optimally quantized offset min-sum algorithm for flexible LDPC decoder.

Daesun Oh, Keshab K. Parhi

Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

2007

Performance of Quantized Min-Sum Decoding Algorithms for Irregular LDPC Codes.

Daesun Oh, Keshab K. Parhi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes.

Daesun Oh, Keshab K. Parhi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Low Complexity Implementations of Sum-Product Algorithm for Decoding Low-Density Parity-Check Codes.

Daesun Oh, Keshab K. Parhi

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Low Complexity Design of High Speed Parallel Decision Feedback Equalizers.

Daesun Oh, Keshab K. Parhi

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006