Daeje Chin

According to our database, Daeje Chin authored at least 4 papers between 1989 and 1994.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

1994

16-Mb synchronous DRAM with 125-Mbyte/s data rate.

Yunho Choi, Myungho Kim, Hyunsoon Jang, Taejin Kim, Seung-hoon Lee, Ho-cheol Lee, Churoo Park, Siyeol Lee, Cheol-soo Kim, Soo-In Cho, Ejaz Haq, J. Karp, Daeje Chin

IEEE J. Solid State Circuits, April, 1994

1993

Variable V/sub CC/ design techniques for battery-operated DRAMs.

Seung-Moon Yoo, Ejaz Haq, Seung-Hoon Lee, Yun-Ho Choi, Soo-In Cho, Nam-Soo Kang, Daeje Chin

IEEE J. Solid State Circuits, April, 1993

1992

Temperature-compensation circuit techniques for high-density CMOS DRAMs.

Dong-Sun Min, Soo-In Cho, Dong Soo Jun, Dong-Jae Lee, Yongsik Seok, Daeje Chin

IEEE J. Solid State Circuits, April, 1992

1989

An experimental 16-Mbit DRAM with reduced peak-current noise.

Daeje Chin, Changhyun Kim, Yunho Choi, Dong-Sun Min, Hong-Sun Hwang, Hoon Choi, Soo-In Cho, Tae-Young Chung, Chan J. Park, Yunseung Shin, Kwang Pyuk Suh, Yong E. Park

IEEE J. Solid State Circuits, October, 1989