Daehyun Kim

Affiliations:
  • Intel Corporation, Santa Clara, CA, USA


According to our database1, Daehyun Kim authored at least 22 papers between 2005 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Bibliography

2014
Improving Communication Performance and Scalability of Native Applications on Intel Xeon Phi Coprocessor Clusters.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

2013
A framework for low-communication 1-D FFT.
Sci. Program., 2013

Efficient backprojection-based synthetic aperture radar computation with many-core processors.
Sci. Program., 2013

Location-aware cache management for many-core processors with deep cache hierarchy.
Proceedings of the International Conference for High Performance Computing, 2013

Tera-scale 1D FFT with low-communication algorithm and Intel® Xeon Phi™ coprocessors.
Proceedings of the International Conference for High Performance Computing, 2013

2012
High Performance Non-uniform FFT on Modern X86-based Multi-core Systems.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
High-Performance 3D Compressive Sensing MRI Reconstruction Using Many-Core Architectures.
Int. J. Biomed. Imaging, 2011

2010
Image Processing on Multicore x86 Architectures.
IEEE Signal Process. Mag., 2010

Fast sort on CPUs and GPUs: a case for bandwidth oblivious SIMD sort.
Proceedings of the ACM SIGMOD International Conference on Management of Data, 2010

Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2009
Mapping High-Fidelity Volume Rendering for Medical Imaging to CPU, GPU and Many-Core Architectures.
IEEE Trans. Vis. Comput. Graph., 2009

2008
Convergence of Recognition, Mining, and Synthesis Workloads and Its Implications.
Proc. IEEE, 2008

Second Life and the New Generation of Virtual Worlds.
Computer, 2008

Atomic Vector Operations on Chip Multiprocessors.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007
Cache-conscious frequent pattern mining on modern and emerging processors.
VLDB J., 2007

Scaling performance of interior-point method on large-scale chip multiprocessor system.
Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, 2007

Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006
Efficient pattern mining on shared memory systems: implications for chip multiprocessor architectures.
Proceedings of the 2006 workshop on Memory System Performance and Correctness, 2006

2005
Cache-conscious Frequent Pattern Mining on a Modern Processor.
Proceedings of the 31st International Conference on Very Large Data Bases, Trondheim, Norway, August 30, 2005

A Characterization of Data Mining Workloads on a Modern Processor.
Proceedings of the Workshop on Data Management on New Hardware, 2005

Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs.
Proceedings of the 42nd Design Automation Conference, 2005


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