Daehwa Paik

According to our database1, Daehwa Paik authored at least 5 papers between 2010 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2015
An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers.
IEEE J. Solid State Circuits, 2015

2013
A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

2011
An analysis on a pseudo-differential dynamic comparator with load capacitance calibration.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010


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