Dae-Woong Park
Orcid: 0000-0003-2755-3935
According to our database1,
Dae-Woong Park
authored at least 15 papers
between 2017 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
High-Power 150/245-GHz Fundamental Oscillators With 12.1/-2.54-dBm Peak Output Power for Phased Array Transceivers.
IEEE J. Solid State Circuits, November, 2024
A D-Band Differential Amplifier With Cross-Couple of Series-Connected Capacitor and Transmission Line-Based Dual-Frequency G<sub>max</sub>-Core.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2024
2023
H-Band Power Amplifiers in 65-nm CMOS by Adopting Output Power Maximized G<sub>max</sub>-Core and Transmission Line-Based Zero-Degree Power Combining Networks.
IEEE J. Solid State Circuits, November, 2023
A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
A 67-mW D-Band FMCW I/Q Radar Receiver With an N-Path Spillover Notch Filter in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
2021
Design of High-Gain Sub-THz Regenerative Amplifiers Based on Double-G<sub>max</sub> Gain Boosting Technique.
IEEE J. Solid State Circuits, 2021
A D-Band Power Amplifier in 65-nm CMOS by Adopting Simultaneous Output Power-and Gain-Matched Gmax-Core.
IEEE Access, 2021
A 67mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28nm CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021
245/243GHz, 9.2/10.5dBm Saturated Output Power, 4.6/2.8% PAE, and 28/26dB Gain Power Amplifiers in 65nm CMOS Adopting 2-and 4-way Power Combining.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 293/440 GHz Push-Push Double Feedback Oscillators with 5.0/-3.9 dBm Output Power and 2.9/0.6 % DC-to-RF Efficiency in 65 nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A 247 and 272 GHz Two-Stage Regenerative Amplifiers in 65 nm CMOS with 18 and 15 dB Gain Based on Double-Gmax Gain Boosting Technique.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A 230-260-GHz Wideband and High-Gain Amplifier in 65-nm CMOS Based on Dual-Peak $G_{{\mathrm{max}}}$ -Core.
IEEE J. Solid State Circuits, 2019
2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
0.5 and 1.5 THz monolithic imagers in a 65 nm CMOS adopting a VCO-based signal processing.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017