Dae Hyun Kwon

According to our database, Dae Hyun Kwon authored at least 16 papers between 2009 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

A Low-Power 28-Gb/s PAM-4MZM Driver With Level Pre-Distortion.

Minkyu Kim, Dae Hyun Kwon, Daewon Rho, Woo-Young Choi

IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020

A Low-Power 40-Gb/s Pre-Emphasis PAM-4 Transmitter With Toggling Serializers.

Dae Hyun Kwon, Minkyu Kim, Sung-Geun Kim, Woo-Young Choi

IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019

A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector.

Dae Hyun Kwon, Minkyu Kim, Sung-Geun Kim, Woo-Young Choi

IEEE Trans. Circuits Syst. II Express Briefs, 2019

2018

A 1.4-to-2.7GHz high-efficiency RF transmitter with an automatic 3FLO-suppression tracking-notch-filter mixer supporting HPUE in 14nm FinFET CMOS.

Qing Liu, Dae Hyun Kwon, Quang-Diep Bui, Jeong-Hyun Choi, Jaehun Lee, Sanghyun Baek, Seungchan Heo, Thomas Byunghak Cho

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

13.3 A SAW-less reconfigurable multimode transmitter with a voltage-mode harmonic-reject mixer in 14nm FinFET CMOS.

Venumadhav Bhagavatula, Dae Hyun Kwon, Jaehun Lee, Quang-Diep Bui, Jeong-Hyun Choi, Siuchuang-Ivan Lu, Sang Won Son

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO.

Sung-Geun Kim, Jinsoo Rhim, Dae Hyun Kwon, Min-Hyeong Kim, Woo-Young Choi

IEEE Trans. Circuits Syst. II Express Briefs, 2016

A Dynamically Biased Multiband 2G/3G/4G Cellular Transmitter in 28 nm CMOS.

Siddharth Seth, Dae Hyun Kwon, Sriramkumar Venugopalan, Sang Won Son, Yongrong Zuo, Venumadhav Bhagavatula, Jaehyun Lim, Dongjin Oh, Thomas Byunghak Cho

IEEE J. Solid State Circuits, 2016

A 5-8 Gb/s low-power transmitter with 2-tap pre-emphasis based on toggling serialization.

Sung-Geun Kim, Tongsung Kim, Dae Hyun Kwon, Woo-Young Choi

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector.

Ki-Hyun Pyun, Dae Hyun Kwon, Woo-Young Choi

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

A clock and data recovery circuit with programmable multi-level phase detector characteristics and a built-in jitter monitor.

Dae Hyun Kwon, Young-Seok Park, Woo-Young Choi

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014

A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation.

Joung-Wook Moon, Sung-Geun Kim, Dae Hyun Kwon, Woo-Young Choi

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2010

Digitally enhanced CMOS RF transmitter with integrated power amplifier

Dae Hyun Kwon

PhD thesis, 2010

A Four-Channel Beamforming Down-Converter in 90-nm CMOS Utilizing Phase-Oversampling.

Richard Tseng, Hao Li, Dae Hyun Kwon, Yun Chiu, Ada S. Y. Poon

IEEE J. Solid State Circuits, 2010

Digitally Equalized CMOS Transmitter Front-End With Integrated Power Amplifier.

Dae Hyun Kwon, Hao Li, Yuchun Chang, Richard Tseng, Yun Chiu

IEEE J. Solid State Circuits, 2010

2009

A Fast Digital Predistortion Algorithm for Radio-Frequency Power Amplifier Linearization With Loop Delay Compensation.

Hao Li, Dae Hyun Kwon, Deming Chen, Yun Chiu

IEEE J. Sel. Top. Signal Process., 2009

CMOS RF transmitter with integrated power amplifier utilizing digital equalization.

Dae Hyun Kwon, Hao Li, Yuchun Chang, Richard Tseng, Yun Chiu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009