Dae Hyun Kim

ACM Trans. Design Autom. Electr. Syst., January, 2024

2023

Dual-Purpose Hardware Algorithms and Architectures - Part 1: Floating-Point Division.

[BibT_eX]

[DOI]

Dae-Hyun Kim

Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023

Dual-Purpose Hardware Algorithms and Architectures - Part 2: Integer Division.

[BibT_eX]

[DOI]

Dae-Hyun Kim

Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023

2022

Design Automation Algorithms for the NP-Separate VLSI Design Methodology.

[BibT_eX]

[DOI]

Monzurul Islam Dewan

ACM Trans. Design Autom. Electr. Syst., 2022

A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

Bayesian Optimization over Permutation Spaces.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022

2021

HeM3D: Heterogeneous Manycore Architecture Based on Monolithic 3D Vertical Integration.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2021

2020

Inter-Tier Process-Variation-Aware Monolithic 3-D NoC Design Space Exploration.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid and Its Applications to VLSI Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

NP-Separate: A New VLSI Design Methodology for Area, Power, and Performance Optimization.

[BibT_eX]

[DOI]

Monzurul Islam Dewan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

RTL-to-GDS Design Tools for Monolithic 3D ICs.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

Saibal Mukhopadhyay

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Power, Performance, and Thermal Trade-offs in M3D-enabled Manycore Chips.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Wire Length Characteristics of Multi-Tier Gate-Level Monolithic 3D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2019

Inter-Tier Process Variation-Aware Monolithic 3D NoC Architectures.

[BibT_eX]

[DOI]

CoRR, 2019

Routing Complexity Minimization of Monolithic Three-Dimensional Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

A Non-Slicing 3-D Floorplan Representation for Monolithic 3-D IC Design.

[BibT_eX]

[DOI]

Shantonu Das

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC Routing.

[BibT_eX]

[DOI]

Proceedings of the 2019 International Symposium on Physical Design, 2019

Dependency-Resolving Intra-Unit Pipeline Architecture for High-Throughput Multipliers.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

High-Throughput Multiplier Architectures Enabled by Intra-Unit Fast Forwarding.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2018

Detailed-Placement-Enabled Dynamic Power Optimization of Multitier Gate-Level Monolithic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Analysis of Performance Benefits of Multitier Gate-Level Monolithic 3-D Integrated Circuits.

[BibT_eX]

[DOI]

Inki Hong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Design Space Exploration of 3D Network-on-Chip: A Sensitivity-based Optimization Approach.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2018

Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on Physical Design, 2018

2017

A legalization algorithm for multi-tier gate-level monolithic three-dimensional integrated circuits.

[BibT_eX]

[DOI]

Yiting Chen

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2016

Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools - Part 2.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

Optimization of dynamic power consumption in multi-tier gate-level monolithic 3D ICs.

[BibT_eX]

[DOI]

Partha Pratim Pande

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory).

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities.

[BibT_eX]

[DOI]

IEEE Des. Test, 2015

Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools.

[BibT_eX]

[DOI]

IEEE Des. Test, 2015

Optimizing 3D NoC Design for Energy Efficiency: A Machine Learning Approach.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Small-World Network Enabled Energy Efficient and Robust 3D NoC Architectures.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Backend Dielectric Reliability Full Chip Simulator.

[BibT_eX]

[DOI]

Muhammad Muqarrab Bashir

IEEE Trans. Very Large Scale Integr. Syst., 2014

TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs.

[BibT_eX]

[DOI]

Saibal Mukhopadhyay

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Simulation of system backend dielectric reliability.

[BibT_eX]

[DOI]

Microelectron. J., 2014

2013

Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout.

[BibT_eX]

[DOI]

Krit Athikulwongse

IEEE Trans. Very Large Scale Integr. Syst., 2013

Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Backend dielectric reliability simulator for microprocessor system.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2012

Design Quality Trade-Off Studies for 3-D ICs Built With Sub-Micron TSVs and Future Devices.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

3D-MAPS: 3D Massively parallel processor with stacked memory.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices.

[BibT_eX]

[DOI]

Kaiyuan Yang

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Block-level 3D IC design with through-silicon-via planning.

[BibT_eX]

[DOI]

Rasit Onur Topaloglu

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Impact of irregular geometries on low-k dielectric breakdown.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2011

Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs.

[BibT_eX]

[DOI]

Suyoun Kim

Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

TSV density-driven global placement for 3D stacked ICs.

[BibT_eX]

[DOI]

Rasit Onur Topaloglu

Proceedings of the International SoC Design Conference, 2011

2010

Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2010

Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs.

[BibT_eX]

[DOI]

Saibal Mukhopadhyay

Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

A study of Through-Silicon-Via impact on the 3D stacked IC layout.

[BibT_eX]

[DOI]

Krit Athikulwongse

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008

Global bus route optimization with application to microarchitectural design exploration.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

Bus-aware microarchitectural floorplanning.

[BibT_eX]

[DOI]