Dae-Hyun Kim
Orcid: 0000-0003-0801-0230Affiliations:
- Samsung Electronics, Hwaseong, Korea
- Georgia Institute of Technology, Atlanta, GA, USA (PhD)
According to our database1,
Dae-Hyun Kim
authored at least 24 papers
between 2007 and 2022.
Collaborative distances:
Collaborative distances:
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Bibliography
2022
A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques.
IEEE J. Solid State Circuits, 2021
25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3<sup>rd</sup>-Generation 10nm DRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown.
IEEE Trans. Very Large Scale Integr. Syst., 2019
2018
Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits.
Microelectron. Reliab., 2017
Analysis of errors in estimating wearout characteristics of time-dependent dielectric breakdown using system-level accelerated life test.
Microelectron. Reliab., 2017
A methodology for estimating memory lifetime using a system-level accelerated life test and error-correcting codes.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
2016
Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
2015
Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs.
Microelectron. Reliab., 2015
Microelectron. Reliab., 2015
The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system.
Microelectron. Reliab., 2015
IEEE Comput. Archit. Lett., 2015
Proceedings of the 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2015
2013
ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
2011
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.
IEEE J. Solid State Circuits, 2011
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2008
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.
IEEE J. Solid State Circuits, 2008
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007