Dae-Han Kwon
Orcid: 0000-0002-2033-8928
According to our database1,
Dae-Han Kwon
authored at least 8 papers
between 2012 and 2023.
Collaborative distances:
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Bibliography
2023
A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application.
IEEE J. Solid State Circuits, 2023
2022
A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE J. Solid State Circuits, 2022
A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2018
A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2016
A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface.
IEEE J. Solid State Circuits, 2016
2012
A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012