Da-Wei Chang
Orcid: 0000-0002-4317-7979
According to our database1,
Da-Wei Chang
authored at least 60 papers
between 1995 and 2024.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
A Hardware Friendly Variation-Tolerant Framework for RRAM-Based Neuromorphic Computing.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024
A Roadside Unit Software Platform for Intelligent Transportation System Applications.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2024
2023
IEEE Commun. Lett., May, 2023
CIMulator: A Comprehensive Simulation Platform for Computing-In-Memory Circuit Macros with Low Bit-Width and Real Memory Materials.
CoRR, 2023
2022
A software framework of roadside units for traffic condition perception and broadcast.
Proceedings of the Conference on Research in Adaptive and Convergent Systems, 2022
RNA-seq Quantification on Processing in memory Architecture: Observation and Characterization.
Proceedings of the 11th IEEE Non-Volatile Memory Systems and Applications Symposium, 2022
2021
Proceedings of the IEEE Symposium on Computers and Communications, 2021
Dual-KV: Improving Performance of Key-value Caches on Multilevel Cell Non-volatile Memory.
Proceedings of the ICPP Workshops 2021: 50th International Conference on Parallel Processing, 2021
2020
Global Clean Page First Replacement and Index-Aware Multistream Prefetcher in Hybrid Memory Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration.
IEEE Trans. Computers, 2019
SSKIP: Lifetime Aware Page Skipping for Multi-Level Cell Flash-based Solid-State Drives.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019
Proceedings of the 2019 IEEE Intl Conf on Dependable, 2019
2018
Proceedings of the 2018 IEEE 42nd Annual Computer Software and Applications Conference, 2018
2017
ROHOM: Requirement-Aware Online Hybrid On-Chip Memory Management for Multicore Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Biomed. Eng., 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
TridentFS: a hybrid file system for non-volatile RAM, flash memory and magnetic disk.
Softw. Pract. Exp., 2016
Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016
2015
ACM Trans. Design Autom. Electr. Syst., 2015
Profit data caching and hybrid disk-aware Completely Fair Queuing scheduling algorithms for hybrid disks.
Softw. Pract. Exp., 2015
2014
ACM Trans. Design Autom. Electr. Syst., 2014
CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
2013
TESA: a temporal and spatial information aware writeback policy for home network-attached storage devices.
IEEE Trans. Consumer Electron., 2013
Concurrent wireless physiological signal monitoring system for multiple freely moving rats.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2013
Proceedings of the 2013 International Conference on Cloud and Green Computing, Karlsruhe, Germany, September 30, 2013
2012
IEEE Trans. Instrum. Meas., 2012
VM aware journaling: improving journaling file system performance in virtualization environments.
Softw. Pract. Exp., 2012
DuLASP: A Workload-Aware Flash Translation Layer Exploiting both Temporal and Spatial Localities.
Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2012
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012
2011
Techniques for improving performance of the FAST (fully-associative sector translation) flash translation layer.
IEEE Trans. Consumer Electron., 2011
ROSE: A Novel Flash Translation Layer for NAND Flash Memory Based on Hybrid Address Translation.
IEEE Trans. Computers, 2011
J. Inf. Sci. Eng., 2011
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
A low cost, low power, high scalability and dependability processor-cluster platform.
Proceedings of the Industrial Embedded Systems (SIES), 2011
Extending Lifetime and Reducing Garbage Collection Overhead of Solid State Disks with Virtual Machine Aware Journaling.
Proceedings of the 17th IEEE International Conference on Parallel and Distributed Systems, 2011
Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011
2010
IEEE Trans. Consumer Electron., 2010
Proceedings of the 10th International Conference on Quality Software, 2010
2009
A Lightweight Buffer Overflow Protection Mechanism with Failure-Oblivious Capability.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2009
2007
Softw. Pract. Exp., 2007
Comments on "Absolute exponential stability of a class of neural networks with unbounded delay".
Neural Networks, 2007
J. Inf. Sci. Eng., 2007
2005
J. Syst. Softw., 2005
A Secure Disk System: Using File System Level Knowledge for Disk Data Protection.
Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005
2003
J. Syst. Softw., 2003
Interference Mitigation Techniques in a High Bandwidth Bluetooth Access Point.
Proceedings of the International Conference on Wireless Networks, 2003
2001
Softw. Pract. Exp., 2001
Int. J. Comput. Math., 2001
2000
1999
Int. J. Comput. Math., 1999
1998
1997
Int. J. Comput. Math., 1997
1995
Int. J. Comput. Math., 1995
Int. J. Comput. Math., 1995
A New Multisplitting Asynchronous Iterative Method for Linear System.
Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing, 1995