Da Eun Shim

Orcid: 0000-0002-2246-1022

According to our database1, Da Eun Shim authored at least 11 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
GNN-based Multi-bit Flip-flop Clustering and Post-clustering Design Optimization for Energy-efficient 3D ICs.
ACM Trans. Design Autom. Electr. Syst., September, 2023

2021
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements.
ACM Trans. Design Autom. Electr. Syst., 2021

FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020
Vortex: OpenCL Compatible RISC-V GPGPU.
CoRR, 2020

Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

A Fault-Tolerant and High-Speed Memory Controller Targeting 3D Flash Memory Cubes for Space Applications.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
A Logic-on-Memory Processor-System Design With Monolithic 3-D Technology.
IEEE Micro, 2019

Tier Partitioning and Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICs.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Logic Monolithic 3D ICs: PPA Benefits and EDA Tools Necessary.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
Road to High-Performance 3D ICs: Performance Optimization Methodologies for Monolithic 3D ICs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018


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