D. Scott Wills

Affiliations:
  • Georgia Institute of Technology, Atlanta GA, USA


According to our database1, D. Scott Wills authored at least 80 papers between 1988 and 2017.

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Bibliography

2017
Parallelizing Multimodal Background Modeling on a Low-Power Integrated GPU.
J. Signal Process. Syst., 2017

Real-time, parallel segmentation of high-resolution images on multi-core platforms.
J. Real Time Image Process., 2017

2014
Multilayer background modeling under occlusions.
Mach. Vis. Appl., 2014

Spatio-temporal multimodal mean.
Proceedings of the 2014 Southwest Symposium on Image Analysis and Interpretation, 2014

2012
Leap segmentation for recovering image surface layout.
Proceedings of the IEEE Southwest Symposium on Image Analysis and Interpretation, 2012

Temporal multi-modal mean.
Proceedings of the IEEE Southwest Symposium on Image Analysis and Interpretation, 2012

Unsupervised video leap segmentation for fast detection of salient segment transformations in mobile sequences.
Proceedings of the 15th International IEEE Conference on Intelligent Transportation Systems, 2012

Accelerating Adaptive Background Modeling on Low-Power Integrated GPUs.
Proceedings of the 41st International Conference on Parallel Processing Workshops, 2012

2011
Color-Aware Instructions for Embedded Superscalar Processors.
J. Signal Process. Syst., 2011

Real-Time Adaptive Background Modeling for Multicore Embedded Systems.
J. Signal Process. Syst., 2011

BigBackground-Based Illumination Compensation for Surveillance Video.
EURASIP J. Image Video Process., 2011

Illumination change compensation techniques to improve kinematic tracking.
Proceedings of the IEEE Workshop on Applications of Computer Vision (WACV 2011), 2011

2010
Cat-Tail DMA: Efficient Image Data Transport for Multicore Embedded Mobile Systems.
J. Mobile Multimedia, 2010

An efficient, chromatic clustering-based background model for embedded vision platforms.
Comput. Vis. Image Underst., 2010

Chromatic Sensitivity of Illumination Change Compensation Techniques.
Proceedings of the Advances in Visual Computing - 6th International Symposium, 2010

2008
An Instruction Throughput Model of Superscalar Processors.
IEEE Trans. Computers, 2008

Bypassing BigBackground: An efficient hybrid background modeling algorithm for embedded video surveillance.
Proceedings of the 2008 Second ACM/IEEE International Conference on Distributed Smart Cameras, 2008

Tracking multiple pedestrians in real-time using kinematics.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2008

2007
The Data Vortex, an All Optical Path Multicomputer Interconnection Network.
IEEE Trans. Parallel Distributed Syst., 2007

Static strands: Safely exposing dependence chains for increasing embedded power efficiency.
ACM Trans. Embed. Comput. Syst., 2007

Multimodal Mean Adaptive Backgrounding for Embedded Real-Time Video Surveillance.
Proceedings of the 2007 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR 2007), 2007

Midground object detection in real world video scenes.
Proceedings of the Fourth IEEE International Conference on Advanced Video and Signal Based Surveillance, 2007

2006
Optimizing Operand Transport using Dynamic SIMDization in Multimedia Systems.
Proceedings of the IEEE 8th Workshop on Multimedia Signal Processing, 2006

2005
Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture.
J. VLSI Signal Process., 2005

Scaling Up the Atlas Chip-Multiprocessor.
IEEE Trans. Computers, 2005

Static strands: safely collapsing dependence chains for increasing embedded power efficiency.
Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, 2005

Reducing Operand Communication Overhead using Instruction Clustering for Multimedia Application.
Proceedings of the Seventh IEEE International Symposium on Multimedia (ISM 2005), 2005

Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Effective detection and elimination of impulse noise for reliable 4: 2: 0 YCbCr signals prior to compression encoding.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

Implementing and Evaluating Color-Aware Instruction Set for Low-Memory, Embedded Video Processing in Data Parallel Architectures.
Proceedings of the Embedded and Ubiquitous Computing, 2005

Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

Architectural Enhancements for Color Image and Video Processing on Embedded Systems.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004
Portable Video Supercomputing.
IEEE Trans. Computers, 2004

The impact of grain size on the efficiency of embedded SIMD image processing architectures.
J. Parallel Distributed Comput., 2004

Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Empirical Analysis of Operand Usage and Transport in Multimedia Applications.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

Efficient Processing of Color Image Sequences Using a Color-Aware Instruction Set on Mobile Systems.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
Modeling technology impact on cluster microprocessor performance.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Fast Color Image Processing Using Quantized Color Instruction Set.
Proceedings of the 2003 International Symposium on Information Technology (ITCC 2003), 2003

Quantized color instruction set for media-on-demand applications.
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003

Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002
On-chip decoupling capacitor optimization using architectural level prediction.
IEEE Trans. Very Large Scale Integr. Syst., 2002

HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction.
IEEE Trans. Parallel Distributed Syst., 2002

Systolic Opportunities for Multidimensional Data Streams.
IEEE Trans. Parallel Distributed Syst., 2002

Estimating Potential Parallelism for Platform Retargeting.
Proceedings of the 9th Working Conference on Reverse Engineering (WCRE 2002), 28 October, 2002

Impulse noise removal on an embedded, low memory SIMD processor.
Proceedings of the 14th International Conference on Digital Signal Processing, 2002

2001
Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications.
IEEE Trans. Computers, 2001

Impact of Pixel per Processor Ratio on Embedded SIMD Architectures.
Proceedings of the 11th International Conference on Image Analysis and Processing (ICIAP 2001), 2001

Cost Modeling or Early Image Processing Applications.
Proceedings of the 2nd International Workshop on Digital and Computational Video (DCV 2001), 2001

2000
Bidirectional single fiber low-cost optoelectronic interconnect for automotive applications.
IEEE Trans. Veh. Technol., 2000

Heterogeneous architecture models for interconnect-motivated system design.
IEEE Trans. Very Large Scale Integr. Syst., 2000

On Dynamic Speculative Thread Partitioning and the MEM-Slicing Algorithm.
J. Univers. Comput. Sci., 2000

Inductive Noise Reduction at the Architectural Level.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999
An architectural solution for the inductive noise problem due to clock-gating.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Adaptive digital bias control for an optical receiver and transmitter.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Fully differential current-input CMOS amplifier front-end suppressing mixed signal substrate noise for optoelectronic applications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications.
Proceedings of the IEEE International Conference On Computer Design, 1999

Exploring Microprocessor Architectures for Gigascale Integration.
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999

Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor.
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999

1998
The Offset Cube: A Three-Dimensional Multicomputer Network Topology Using Through-Wafer Optics.
IEEE Trans. Parallel Distributed Syst., 1998

Retrospective: the J-machine.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Architecture of a Message-Driven Processor.
Proceedings of the 25 Years of the International Symposia on Computer Architecture (Selected Papers)., 1998

Profiling for input predictable threads.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997
High-Throughput, Low-Memory Applications on the Pica Architecture.
IEEE Trans. Parallel Distributed Syst., 1997

A 100 Mbps, LED Through-Wafer Optoelectronic Link for Multicomputer Interconnection Networks.
J. Parallel Distributed Comput., 1997

HiPER-P: An Efficient, High-Performance Router for Multicomputer Interconnection Networks.
Proceedings of the Parallel Computer Routing and Communication, 1997

1996
Modeling the Technology Impact on the Design of a Two-Level Multicomputer Interconnection Network.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Real-Time Implementation of Full-Search Vector Quantization on a Low Memory SIMD Architecture.
Proceedings of the 6th Data Compression Conference (DCC '96), Snowbird, Utah, USA, March 31, 1996

Incorporating Multi-Chip Module Packaging Constraints into System Design.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Parallelized formulation of the maximum likelihood-expectation maximization algorithm for fine-grain message-passing architectures.
IEEE Trans. Medical Imaging, 1995

Hoisting Branch Conditions - Improving Super-Scalar Processor Performance.
Proceedings of the Languages and Compilers for Parallel Computing, 1995

Silicon VLSI processing architectures incorporating integrated optoelectronic devices.
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994
The Offset Cube: An Optoelectronic Interconnection Network.
Proceedings of the Parallel Computer Routing and Communication, 1994

1993
A Scalable Optical Interconnection Network for Fine-Grain Parallel Architectures.
Proceedings of the 1993 International Conference on Parallel Processing, 1993

Pica: An Ultra-Light Processor for High-Througput Applications.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992
The Message Driven Processor: An Integrated Multicomputer Processing Element.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1989
Universal Mechanisms for Concurrency.
Proceedings of the PARLE '89: Parallel Architectures and Languages Europe, 1989

The J-Machine: A Fine-Gain Concurrent Computer.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

1988
Tokenless static data flow using associative templates.
Proceedings of the Proceedings Supercomputing '88, Orlando, FL, USA, November 12-17, 1988, 1988


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