D. R. Vasanthi
Orcid: 0000-0001-9627-2913
According to our database1,
D. R. Vasanthi
authored at least 6 papers
between 2016 and 2024.
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Bibliography
2024
HRM: M-Term Heterogeneous Hybrid Blend Recursive Multiplier for GF(2<sup>n</sup>) Polynomial.
IEEE Trans. Very Large Scale Integr. Syst., August, 2024
Hardware-Efficient ECC Processor Design using Non-Homogeneous Split Hybrid Karatsuba Multiplier.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
2023
Design and Evaluation of M-Term Non-Homogeneous Hybrid Karatsuba Polynomial Multiplier.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
MNHOKA - PPA Efficient M-Term Non-Homogeneous Hybrid Overlap-free Karatsuba Multiplier for GF (2<sup>n</sup>) Polynomial Multiplier.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
2018
Implementation of Robust Solid State Drive Controller Using LZ77 Compression and SHA-1 Encryption Technique.
Proceedings of the Intelligent Systems Design and Applications, 2018
2016
Implementation of Robust Compression Technique Using LZ77 Algorithm on Tensilica's Xtensa Processor.
Proceedings of the 2016 International Conference on Information Technology, 2016