D. Mahaveer Sathaiya

According to our database, D. Mahaveer Sathaiya authored at least 3 papers between 2023 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

On the Extreme Scaling of Transistors with Monolayer MOS2 Channel.

Wen-Chia Wu, Terry Y. T. Hung, D. Mahaveer Sathaiya, Edward Chen, Chen-Feng Hsu, Walker Yun, Hsiang-Chi Hu, Bo-Heng Liu, T. Y. Lee, Chi-Chung Kei, Wen-Hao Chang, Jin Cai, W. Jeff, Chung-Cheng Wu, H.-S. Philip Wong, Chao-Hsin Chien, Chao-Ching Cheng, Iuliana P. Radu

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

Scaled contact length with low contact resistance in monolayer 2D channel transistors.

Wen-Chia Wu, Terry Y. T. Hung, D. Mahaveer Sathaiya, Dongxu Fan, Goutham Arutchelvan, Chen-Feng Hsu, Sheng-Kai Su, Ang-Sheng Chou, Edward Chen, Weisheng Li, Zhihao Yu, Hao Qiu, Ying-Mei Yang, Kuang-I Lin, Yun-Yang Shen, Wen-Hao Chang, San Lin Liew, Vincent D.-H. Hou, Jin Cai, Chung-Cheng Wu, Jeff Wu, H.-S. Philip Wong, Xinran Wang, Chao-Hsin Chien, Chao-Ching Cheng, Iuliana P. Radu

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Building high performance transistors on carbon nanotube channel.

Gregory Pitner, Nathaniel Safron, Tzu-Ang Chao, Shengman Li, Sheng-Kai Su, Gilad Zeevi, Qing Lin, Hsin-Yuan Chiu, Matthias Passlack, Zichen Zhang, D. Mahaveer Sathaiya, Aslan Wei, Carlo Gilardi, Edward Chen, San Lin Liew, Vincent D.-H. Hou, Chung-Wei Wu, Jeff Wu, Zhiwei Lin, Jeffrey Fagan, Ming Zheng, Han Wang, Subhasish Mitra, H.-S. Philip Wong, Iuliana P. Radu

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023