D. Gracia Nirmala Rani

Orcid: 0000-0001-7974-1183

According to our database1, D. Gracia Nirmala Rani authored at least 10 papers between 2013 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2022
A C4.5 decision tree classifier based floorplanning algorithm for System-on-Chip design.
Microelectron. J., 2022

An Enhanced Memetic Algorithm using SKB tree representation for fixed-outline and temperature driven non-slicing floorplanning.
Integr., 2022

Design and analysis of 28 GHz CMOS low power LNA with 6.4 dB gain variability for 5G applications.
Trans. Emerg. Telecommun. Technol., 2022

2021
Design of 5-bit Flash ADC Using 180 nm Technology for Medical Applications.
Wirel. Pers. Commun., 2021

Design and analysis of a sleep and wake-up CMOS low noise amplifier for 5G applications.
Telecommun. Syst., 2021

2020
Design and analysis of 0.9 and 2.3-GHz concurrent dual-band CMOS LNA for mobile communication.
Int. J. Circuit Theory Appl., 2020

2019
Design and optimisation of feedforward noise cancelling complementary metal oxide semiconductor LNA for 2.4 GHz WLAN applications.
IET Circuits Devices Syst., 2019

2018
Design of CMOS Based Biosensor for Implantable Medical Devices.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

Design of CMOS based LNA for 5G Wireless Applications.
Proceedings of the 6th International Conference on Communications and Broadband Networking, 2018

2013
A survey on B*-Tree-based evolutionary algorithms for VLSI floorplanning optimisation.
Int. J. Comput. Appl. Technol., 2013


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