D. A. Tran

According to our database, D. A. Tran authored at least 4 papers between 2010 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems.

D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich

J. Electron. Test., 2014

2012

A pseudo-dynamic comparator for error detection in fault tolerant architectures.

D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

2011

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits.

D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Parity prediction synthesis for nano-electronic gate designs.

D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich

Proceedings of the 2011 IEEE International Test Conference, 2010