Cyrus Bamji

According to our database1, Cyrus Bamji authored at least 21 papers between 1985 and 2004.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2004
A Time-Of-Flight Depth Sensor - System Description, Issues and Solutions.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2004

2001
Technology mapping for high-performance static CMOS and pass transistor logic designs.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Fast and accurate timing characterization using functionalinformation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

An Advanced Timing Characterization Method Using Mode Dependency.
Proceedings of the 38th Design Automation Conference, 2001

2000
Transistor-Level Timing Analysis Using Embedded Simulation.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999
Functional Timing Analysis for IP Characterization.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Interleaving buffer insertion and transistor sizing into a single optimization.
IEEE Trans. Very Large Scale Integr. Syst., 1998

Incremental Autojogging using Range Spaces.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

An Improved Cost Heuristic for Transistor Sizing.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Combined transistor sizing with buffer insertion for timing optimization.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997
Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs.
Proceedings of the 1997 International Symposium on Physical Design, 1997

1996
Enhanced Network Flow Algorithm for Yield Optimization.
Proceedings of the 33st Conference on Design Automation, 1996

1994
GLOVE: A Graph-Based Layout Verifier.
Proceedings of the Seventh International Conference on VLSI Design, 1994

1993
MSTC: A Method for Identifying Overconstraints during Hierarchical Compaction.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Cloning techniques for hierarchical compaction.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Hierarchical Pitchmatching Compaction Using Minimum Design.
Proceedings of the 29th Design Automation Conference, 1992

1989
Graph-based representations and coupled verification of VLSI schematics and layouts.
PhD thesis, 1989

GRASP: A Grammar-based Schematic Parser.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1985
The systematic exploration of pipelined array multiplier performance.
Proceedings of the IEEE International Conference on Acoustics, 1985

A design by example regular structure generator.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985


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