Cyril Prasanna Raj

According to our database1, Cyril Prasanna Raj authored at least 9 papers between 2009 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Novel DWT/IDWT Architecture for 3D with Nine Stage 2D Parallel Processing using Split Distributed Arithmetic.
Int. J. Image Graph., 2020

2018
High Speed Area Optimized Hybrid DA Architecture for 2D-DTCWT.
Int. J. Image Graph., 2018

2017
High speed modular systolic array-based DTCWT with parallel processing architecture for 2D image transformation on FPGA.
Int. J. Wavelets Multiresolution Inf. Process., 2017

2010
FPGA Based Reconfigurable 200 MHz Transmitter and Receiver Front End for MIMO-OFDM.
Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, 2010

Analysis of Wavelet for 3D-DWT Volumetric Image Compression.
Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, 2010

Design and VLSI Implementation of Interpolators/Decimators for DUC/DDC.
Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, 2010

VLSI Architecuture for Neural Network Based Image Compression.
Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, 2010

Design and Verification of Cache Memory Decoder for High Speed Multicore Processor.
Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, 2010

2009
VLSI Design and Analysis of Multipliers for Low Power.
Proceedings of the Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2009), 2009


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