Cynthia Hsu
According to our database1,
Cynthia Hsu
authored at least 8 papers
between 2008 and 2023.
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Bibliography
2023
IEEE J. Solid State Circuits, 2023
2022
A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs.
IEEE J. Solid State Circuits, 2021
2020
13.5 A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75µs and tR=4µs.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2012
128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2009
A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008