Cunxi Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs.

[BibT_eX]

[DOI]

CoRR, 2023

DAG-aware Synthesis Orchestration.

[BibT_eX]

[DOI]

CoRR, 2023

Rubik's Optical Neural Networks: Multi-task Learning with Physics-aware Rotation Architecture.

[BibT_eX]

[DOI]

CoRR, 2023

Accelerating Exact Combinatorial Optimization via RL-based Initialization - A Case Study in Scheduling.

[BibT_eX]

[DOI]

Jiaqi Yin

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

AIM: Accelerating Arbitrary-Precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Invited Paper: Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Physics-aware Roughness Optimization for Diffractive Optical Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

RESPECT: Reinforcement Learning based Edge Scheduling on Pipelined Coral Edge TPUs.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Equality Saturation for Datapath Synthesis: A Pathway to Pareto Optimality.

[BibT_eX]

[DOI]

Ecenur Ustun

Zhiru Zhang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

LightRidge: An End-to-end Agile Design Framework for Diffractive Optical Neural Networks.

[BibT_eX]

[DOI]

Berardi Sensale Rodriguez

Ruiyang Chen

Minhan Lou

Berardi Sensale Rodriguez

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022

Physics-informed recurrent neural network for time dynamics in optical resonances.

[BibT_eX]

[DOI]

Nat. Comput. Sci., 2022

Device-system Co-design of Photonic Neuromorphic Processor using Reinforcement Learning.

[BibT_eX]

[DOI]

CoRR, 2022

Physics-aware Complex-valued Adversarial Machine Learning in Reconfigurable Diffractive All-optical Neural Network.

[BibT_eX]

[DOI]

CoRR, 2022

End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit.

[BibT_eX]

[DOI]

Walter Lau Neto

CoRR, 2022

Exact Memory- and Communication-aware Scheduling of DNNs on Pipelined Edge TPUs.

[BibT_eX]

[DOI]

Jiaqi Yin

Zhiru Zhang

Proceedings of the 7th IEEE/ACM Symposium on Edge Computing, 2022

Physics-Aware Differentiable Discrete Codesign for Diffractive Optical Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

IMpress: Large Integer Multiplication Expression Rewriting for FPGA HLS.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

2021

SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Late Breaking Results: Physical Adversarial Attacks of Diffractive Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization.

[BibT_eX]

[DOI]

Walter Lau Neto

Matheus Trevisan Moreira

Luca G. Amarù

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Multi-Task Learning in Diffractive Deep Neural Networks via Hardware-Software Co-design.

[BibT_eX]

[DOI]

Berardi Sensale Rodriguez

Ruiyang Chen

CoRR, 2020

Artificial Intelligence Accelerators based on Graphene Optoelectronic Devices.

[BibT_eX]

[DOI]

Ruiyang Chen

CoRR, 2020

Contrastive Weight Regularization for Large Minibatch SGD.

[BibT_eX]

[DOI]

CoRR, 2020

Decision Making in Synthesis cross Technologies using LSTMs and Transfer Learning.

[BibT_eX]

[DOI]

Wang Zhou

Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

FlowTune: Practical Multi-armed Bandits in Boolean Optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019

Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets.

[BibT_eX]

[DOI]

Zhiru Zhang

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Spectral approach to verifying non-linear arithmetic circuits.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Fast Algebraic Rewriting Based on And-Inverter Graphs.

[BibT_eX]

[DOI]

Alan Mishchenko

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Survey on Applications of Formal Methods in Reverse Engineering and Intellectual Property Protection.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2018

Performance Estimation of Synthesis Flows cross Technologies using LSTMs and Transfer Learning.

[BibT_eX]

[DOI]

Wang Zhou

CoRR, 2018

Algorithmic Obfuscation over GF(2<sup>m</sup>).

[BibT_eX]

[DOI]

Daniel E. Holcomb

CoRR, 2018

Formal Analysis of Galois Field Arithmetics - Parallel Verification and Reverse Engineering.

[BibT_eX]

[DOI]

CoRR, 2018

Rewriting Environment for Arithmetic Circuit Verification.

[BibT_eX]

[DOI]

Proceedings of the LPAR-22. 22nd International Conference on Logic for Programming, 2018

Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

End-to-End Industrial Study of Retiming.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Developing synthesis flows without human knowledge.

[BibT_eX]

[DOI]

Houping Xiao

Giovanni De Micheli

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Advanced datapath synthesis using graph isomorphism.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Reverse engineering of irreducible polynomials in GF(2<sup>m</sup>) arithmetic.

[BibT_eX]

[DOI]

Daniel E. Holcomb

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Efficient parallel verification of Galois field multipliers.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Formal Verification of Arithmetic Circuits by Function Extraction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Reverse Engineering of Irreducible Polynomials in GF(2^m) Arithmetic.

[BibT_eX]

[DOI]

Daniel E. Holcomb

CoRR, 2016

Formal Verification Using Don't-Care and Vanishing Polynomials.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Analyzing Imprecise Adders Using BDDs - A Case Study.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Automatic word-level abstraction of datapath.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuits.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

DAG-aware logic synthesis of datapaths.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Logic Debugging of Arithmetic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Verification of arithmetic datapath designs using word-level approach - A case study.

[BibT_eX]

[DOI]

Walter Brown