Cunlu Li
Orcid: 0000-0002-3724-6878
According to our database1,
Cunlu Li
authored at least 30 papers
between 2015 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
J. Parallel Distributed Comput., April, 2024
DRLAR: A deep reinforcement learning-based adaptive routing framework for network-on-chips.
Comput. Networks, 2024
Xraytest: An X-ray Test system for finding faults of RDMA-NIC Design and Implementation.
Proceedings of the 2024 SIGCOMM Workshop on Networks for AI Computing, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
LARE: A Linear Approximate Reinforcement Learning Based Adaptive Routing for Network-on-Chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Poster Abstract: A Network-on-Chip Router Architecture for Industrial Internet-of-Thing Gateways.
Proceedings of the 22nd International Conference on Information Processing in Sensor Networks, 2023
Proceedings of the Euro-Par 2023: Parallel Processing - 29th International Conference on Parallel and Distributed Computing, Limassol, Cyprus, August 28, 2023
2022
IEEE Trans. Computers, 2022
ACM Trans. Archit. Code Optim., 2022
Revisiting network congestion avoidance through adaptive packet-chaining reservation.
Comput. Networks, 2022
Proceedings of the 24th IEEE Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, 2022
2021
ACM Trans. Archit. Code Optim., 2021
Proceedings of the Network and Parallel Computing, 2021
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021
2020
DancerFly: An Order-Aware Network-on-Chip Router On-the-Fly Mitigating Multi-path Packet Reordering.
Int. J. Parallel Program., 2020
DBM: A Dimension-Bubble-Based Multicast Routing Algorithm for 2D Mesh Network-on-Chips.
Proceedings of the Advanced Computer Architecture - 13th Conference, 2020
2019
HARE: History-Aware Adaptive Routing Algorithm for Endpoint Congestion in Networks-on-Chip.
Int. J. Parallel Program., 2019
DeepHiR: improving high-radix router throughput with deep hybrid memory buffer microarchitecture.
Proceedings of the ACM International Conference on Supercomputing, 2019
Proceedings of the 48th International Conference on Parallel Processing, 2019
2018
IEEE Trans. Parallel Distributed Syst., 2018
Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018
Proceedings of the 37th IEEE International Performance Computing and Communications Conference, 2018
Eca-Router : On Achieving Endpoint Congestion Aware Switch Allocation in the On-Chip Network.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
2017
Proceedings of the ACM Turing 50th Celebration Conference, 2017
2016
Galaxyfly: A Novel Family of Flexible-Radix Low-Diameter Topologies for Large-Scales Interconnection Networks.
Proceedings of the 2016 International Conference on Supercomputing, 2016
Discovering Multi-type Correlated Events with Time Series for Exception Detection of Complex Systems.
Proceedings of the IEEE International Conference on Data Mining Workshops, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
RoB-Router: Low Latency Network-on-Chip Router Microarchitecture Using Reorder Buffer.
Proceedings of the 24th IEEE Annual Symposium on High-Performance Interconnects, 2016
Proceedings of the 2016 IEEE International Conference on Cluster Computing, 2016
2015
HVCRouter: Energy Efficient Network-on-Chip Router with Heterogeneous Virtual Channels.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015