Csaba Andras Moritz

IEEE Trans. Parallel Distributed Syst., April, 2023

Compact Model Parameter Extraction using Bayesian Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

2022

Technology Development and Modeling of Switching Lattices Using Square and H Shaped Four-Terminal Switches.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

Hardware-accelerated Simulation-based Inference of Stochastic Epidemiology Models for COVID-19.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

2021

Architecting for Artificial Intelligence with Emerging Nanotechnology.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2021

Efficient State-space Exploration in Massively Parallel Simulation Based Inference.

[BibT_eX]

[DOI]

CoRR, 2021

SkyBridge-3D-CMOS 2.0: IC Technology for Stacked-Transistor 3D ICs beyond FinFETs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

A Wafer-scale Manufacturing Pathway for Fine-grained Vertical 3D-IC Technology.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2020

Accelerating Simulation-based Inference with Emerging AI Hardware.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Rebooting Computing, 2020

Nano-Crossbar based Computing: Lessons Learned and Future Directions.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Reconfigurable Probabilistic AI Architecture for Personalized Cancer Treatment.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Conference on Rebooting Computing, 2019

Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling.

[BibT_eX]

[DOI]

Serzat Safaltin

Oguz Gencer

Muhammed Ceylan Morgül

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Integrated Synthesis Methodology for Crossbar Arrays.

[BibT_eX]

[DOI]

Muhammed Ceylan Morgül

Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

2017

NP-Dynamic Skybridge: A Fine-Grained 3D IC Technology with NP-Dynamic Logic.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2017

Power-delivery network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS.

[BibT_eX]

[DOI]

Jiajun Shi

Mingyu Li

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Fine-grained 3D reconfigurable computing fabric with RRAM.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

SkyNet: Memristor-based 3D IC for artificial neural networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Structure Discovery for Gene Expression Networks with Emerging Stochastic Hardware.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Magneto-Electric Approximate Computational Circuits for Bayesian Inference.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Rebooting Computing, 2017

2016

Routability in 3D IC design: Monolithic 3D vs. Skybridge 3D CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Towards automatic thermal network extraction in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Skybridge-3D-CMOS: A Vertically-Composed Fine-Grained 3D CMOS Integrated Circuit Technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015

Welcome Message.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2015

Nanowire Volatile RAM as an Alternative to SRAM.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2015

Low-Power Heterogeneous Graphene Nanoribbon-CMOS Multistate Volatile Memory Circuit.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2015

Manufacturing Pathway and Experimental Demonstration for Nanoscale Fine-Grained 3-D Integrated Circuit Fabric.

[BibT_eX]

[DOI]

CoRR, 2015

Self-similar Magneto-electric Nanocircuit Technology for Probabilistic Inference Engines.

[BibT_eX]

[DOI]

Mingyu Li

Mohammad Salehi Fashami

Ayan Kumar Biswas

Jayasimha Atulasimha

Supriyo Bandyopadhyay

CoRR, 2015

Architecting for Causal Intelligence at Nanoscale.

[BibT_eX]

[DOI]

Mohammad Salehi Fashami

Jayasimha Atulasimha

Supriyo Bandyopadhyay

Computer, 2015

Architecting NP-Dynamic Skybridge.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Architecting 3-D integrated circuit fabric with intrinsic thermal management features.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Architecting connectivity for fine-grained 3-D vertically integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Physically equivalent magneto-electric nanoarchitecture for probabilistic reasoning.

[BibT_eX]

[DOI]

Mingyu Li

Mohammad Salehi Fashami

Ayan Kumar Biswas

Jayasimha Atulasimha

Supriyo Bandyopadhyay

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Fine-grained 3-D integrated circuit fabric using vertical nanowires.

[BibT_eX]

[DOI]

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014

Parameter variation sensing and estimation in nanoscale fabrics.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2014

Introduction to JPDC special issue on computing with future nanotechnology.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2014

Heterogeneous graphene-CMOS ternary content addressable memory.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2014

Metal-Gated Junctionless Nanowire Transistors.

[BibT_eX]

[DOI]

CoRR, 2014

Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS.

[BibT_eX]

[DOI]

CoRR, 2014

A new Tunnel-FET based RAM concept for ultra-low power applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Wave-based multi-valued computation framework.

[BibT_eX]

[DOI]

Sankara Narayanan Rajapandian

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

2013

Variability in Nanoscale Fabrics: Bottom-up Integrated Analysis and Mitigation.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2013

Design of 8T-nanowire RAM array.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Experimental prototyping of beyond-CMOS nanowire computing fabrics.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Embedded processors based on Spin Wave Functions (SPWFs).

[BibT_eX]

[DOI]

Sankara Narayanan Rajapandian

Prasad Shabadi

Jiajun Shi

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Nanowire field-programmable computing platform.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

2012

Ternary volatile random access memory based on heterogeneous graphene-CMOS fabric.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Spin wave nanofabric update.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

2011

Energy-Efficient Hardware Data Prefetching.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Parametrized hardware architectures for the Lucas primality test.

[BibT_eX]

[DOI]

Adrien Le Masle

Wayne Luk

Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Spin wave functions nanofabric update.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

N3ASICs: Designing nanofabrics with fine-grained CMOS integration.

[BibT_eX]

[DOI]

Pavan Panchapakeshan

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Nanoscale Application Specific Integrated Circuits.

[BibT_eX]

[DOI]

Jorge Kina

Pavan Panchapakeshan

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Hybrid Graphene Nanoribbon-CMOS tunneling volatile memory fabric.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Biased Voting for Improved Yield in Nanoscale Fabrics.

[BibT_eX]

[DOI]

Md. Muwyid U. Khan

Israel Koren

C. Mani Krishna

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010

Programmable cellular architectures at the nanoscale.

[BibT_eX]

[DOI]

Teng Wang

Nano Commun. Networks, 2010

Towards logic functions as the device.

[BibT_eX]

[DOI]

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009

Towards a framework for designing applications onto hybrid nano/CMOS fabrics.

[BibT_eX]

[DOI]

Microelectron. J., 2009

Validating cascading of crossbar circuits with an integrated device-circuit exploration.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

2008

Data Memory Subsystem Resilient to Process Variations.

[BibT_eX]

[DOI]

Mahmoud A. Bennaser

IEEE Trans. Very Large Scale Integr. Syst., 2008

Synchronization coherence: A transparent hardware mechanism for cache coherence and fine-grained synchronization.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2008

Power and performance tradeoffs with process variation resilient adaptive cache architectures.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Impact of Process Variation in Fault-Resilient Streaming Nanoprocessors.

[BibT_eX]

[DOI]

Proceedings of the Nano-Net - Third International ICST Conference, 2008

CMOS Control Enabled Single-Type FET NASIC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007

Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Support for Fine-Grained Synchronization in Shared-Memory Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the Parallel Computing Technologies, 2007

Combining 2-level logic families in grid-based nanoscale fabrics.

[BibT_eX]

[DOI]

Teng Wang

Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

Designing Memory Subsystems Resilient to Process Variations.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2006

Power and Failure Analysis of CAM Cells Due to Process Variations.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005

PARE: a power-aware hardware data prefetching engine.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

2004

Coupling compiler-enabled and conventional memory accessing for energy efficiency.

[BibT_eX]

[DOI]

Raksit Ashok

Saurabh Chheda

ACM Trans. Comput. Syst., 2004

Energy-Aware Data Prefetching for General-Purpose Programs.

[BibT_eX]

[DOI]

Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004

Energy Characterization of Hardware-Based Data Prefetching.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Opportunities and challenges in application-tuned circuits and architectures based on nanodevices.

[BibT_eX]

[DOI]

Teng Wang

Zhenghua Qi

Proceedings of the First Conference on Computing Frontiers, 2004

Combining compiler and runtime IPC predictions to reduce energy in next generation architectures.

[BibT_eX]

[DOI]

Proceedings of the First Conference on Computing Frontiers, 2004

Cool-Fetch: A Compiler-Enabled IPC Estimation Based Framework for Energy Reduction.

[BibT_eX]

[DOI]

Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004

2003

Cool-Cache: A compiler-enabled energy efficient data caching framework for embedded/multimedia processors.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2003

Runtime Biased Pointer Reuse Analysis and Its Application to Energy Efficiency.

[BibT_eX]

[DOI]

Saurabh Chheda

Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003

2002

Cool-Fetch: Compiler-Enabled Power-Aware Fetch Throttling.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2002

The Minimax Cache: An Energy-Efficient Framework for Media Processors.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Cool-Mem: combining statically speculative memory accessing with selective address translation for energy efficiency.

[BibT_eX]

[DOI]

Raksit Ashok

Saurabh Chheda

Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), 2002

2001

SimpleFit: A Framework for Analyzing Design Trade-Offs in Raw Architectures.

[BibT_eX]

[DOI]

Donald Yeung

Anant Agarwal

IEEE Trans. Parallel Distributed Syst., 2001

LoGPC: Modeling Network Contention in Message-Passing Programs.

[BibT_eX]

[DOI]

Matthew I. Frank

IEEE Trans. Parallel Distributed Syst., 2001

Performance Modeling and Evaluation of MPI.

[BibT_eX]

[DOI]

Khalid Al-Tawil

J. Parallel Distributed Comput., 2001

Cool-cache for hot multimedia.

[BibT_eX]

[DOI]

Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

2000

FlexCache: A Framework for Flexible Compiler Generated Data Caching.

[BibT_eX]

[DOI]

Matthew I. Frank

Saman P. Amarasinghe

Proceedings of the Intelligent Memory Systems, Second International Workshop, 2000

1999

Parallelizing Applications into Silicon.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998

LogGP Quantified: The Case for MPI.

[BibT_eX]

[DOI]

Khalid Al-Tawil

Proceedings of the Seventh IEEE International Symposium on High Performance Distributed Computing, 1998

Exploring Optimal Cost-Performance Designs for Raw Microprocessors.

[BibT_eX]

[DOI]

Donald Yeung

Anant Agarwal

Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

The effects of pipelined communication in message-passing.

[BibT_eX]

Proceedings of the Computers and Their Applications (CATA-98), 1998

1997

A static mapping system for logically shared memory parallel programs.

[BibT_eX]