Cristina Silvano

Andrea Bartolini

Andrea Rosario Beccari

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Application Adaptation at Runtime through Dynamic Knobs Autotuning.

[BibT_eX]

[DOI]

Davide Gadioli

Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016

Automatic Pruning of Autotuning Parameter Space for OpenCL Applications.

[BibT_eX]

[DOI]

Ahmet Erdem

Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016

An Evaluation of Autotuning Techniques for the Compiler Optimization Problems.

[BibT_eX]

[DOI]

Amir Hossein Ashouri

Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016

The ANTAREX approach to autotuning and adaptivity for energy efficient HPC systems.

[BibT_eX]

[DOI]

Andrea Rosario Beccari

Radim Cmar

Erven Rohou

Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Variability-Aware Voltage Island Management for Near-Threshold Computing with Performance Guarantees.

[BibT_eX]

[DOI]

Ioannis S. Stamelakos

Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016

2015

SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

DeSpErate++: An Enhanced Design Space Exploration Framework Using Predictive Simulation Scheduling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

ViPES 2015 - Preface.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Application autotuning to support runtime adaptivity in multicore architectures.

[BibT_eX]

[DOI]

Davide Gadioli

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Significant papers from the first 25 years of the FPL conference.

[BibT_eX]

[DOI]

Philip Heng Wai Leong

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Preface.

[BibT_eX]

[DOI]

Peter Y. K. Cheung

Wayne Luk

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

ANTAREX - AutoTuning and Adaptivity appRoach for Energy Efficient eXascale HPC Systems.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

2014

A Configurable Monitoring Infrastructure for NoC-Based Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Combining application adaptivity and system-wide Resource Management on multi-core platforms.

[BibT_eX]

[DOI]

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

OpenCL Application Auto-tuning and Run-Time Resource Management for Multi-core Platforms.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

A Bayesian network approach for compiler auto-tuning for embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

Voltage island management in near threshold manycore architectures to mitigate dark silicon.

[BibT_eX]

[DOI]

Ioannis S. Stamelakos

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Variation-aware voltage island formation for power efficient near-threshold manycore architectures.

[BibT_eX]

[DOI]

Ioannis S. Stamelakos

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

DRuiD: Designing reconfigurable architectures with decision-making support.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013

Design-space exploration and runtime resource management for multicores.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

ARTE: An Application-specific Run-Time managEment framework for multi-cores based on queuing models.

[BibT_eX]

[DOI]

Parallel Comput., 2013

Special issue DSD 2012 on Reliability and dependability in MPSoC Technologies.

[BibT_eX]

[DOI]

Smaïl Niar

Microprocess. Microsystems, 2013

A framework for Compiler Level statistical analysis over customized VLIW architecture.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Run-time optimization of a dynamically reconfigurable embedded system through performance prediction.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A meta-model assisted coprocessor synthesis framework for compiler/architecture parameters customization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Thermal-aware datapath merging for coarse-grained reconfigurable processors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Improving simulation speed and accuracy for many-core embedded platforms with ensemble models.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2012

Architecture Optimization of Application-Specific Implicit Instructions.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2012

OSCAR: An Optimization Methodology Exploiting Spatial Correlation in Multicore Design Spaces.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Floorplan-aware hierarchical NoC topology with GALS interfaces.

[BibT_eX]

[DOI]

Altamiro Amadeu Susin

Luigi Carro

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach.

[BibT_eX]

[DOI]

Proceedings of the 2012 Interconnection Network Architecture, 2012

Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Evaluating Run-time Resource Management Policies for Multi-core Embedded Platforms with the EMME Evaluation Framework.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012

2011

Linking run-time resource management of embedded multi-core platforms with automated design-time exploration.

[BibT_eX]

[DOI]

Fernanda Lima Kastensmidt

IET Comput. Digit. Tech., 2011

Two-levels of adaptive buffer for virtual channel router in NoCs.

[BibT_eX]

[DOI]

Caroline Concatto

Anelise Kologeski

Luigi Carro

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

ARTE: An Application-specific Run-Time management framework for multi-core systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach.

[BibT_eX]

[DOI]

Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip.

[BibT_eX]

[DOI]

Altamiro Amadeu Susin

Luigi Carro

Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011

The MULTICUBE Design Flow.

[BibT_eX]

[DOI]

Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011

Conclusions.

[BibT_eX]

[DOI]

Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011

Optimization Algorithms for Design Space Exploration of Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011

Response Surface Modeling for Design Space Exploration of Embedded System.

[BibT_eX]

[DOI]

Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011

Design Space Exploration for Run-Time Management of a Reconfigurable System for Video Streaming.

[BibT_eX]

[DOI]

Giovanni Mariani

Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011

Design Space Exploration of Parallel Architectures.

[BibT_eX]

[DOI]

Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011

Design Space Exploration Supporting Run-Time Resource Management.

[BibT_eX]

[DOI]

Prabhat Avasare

Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011

2010

A monitoring system for NoCs.

[BibT_eX]

[DOI]

Proceedings of the Third International Workshop on Network on Chip Architectures, 2010

MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures.

[BibT_eX]

[DOI]

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.

[BibT_eX]

[DOI]

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

An industrial design space exploration framework for supporting run-time resource management on multi-core systems.

[BibT_eX]

[DOI]

Giovanni Mariani

Prabhat Avasare

Geert Vanmeerbeeck

Proceedings of the Design, Automation and Test in Europe, 2010

Energy-performance design space exploration in SMT architectures exploiting selective load value predictions.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

A correlation-based design space exploration methodology for multi-processor systems-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Multicube Explorer: An Open Source Framework for Design Space Exploration of Chip Multi-Processors.

[BibT_eX]

[DOI]

Proceedings of the ARCS '10, 2010

2009

ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A design space exploration methodology supporting run-time resource management for multi-processor Systems-on-chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

Yield enhancement by robust application-specific mapping on Network-on-Chips.

[BibT_eX]

[DOI]

Proceedings of the Second International Workshop on Network on Chip Architectures, 2009

Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

MPSoCs run-time monitoring through Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Variability-aware robust design space exploration of chip multiprocessor architectures.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Secure Memory Accesses on Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on Application Specific Processors, 2008

An efficient design space exploration methodology for multiprocessor SoC architectures based on response surface methods.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Dynamic configuration of application-specific implicit instructions for embedded pipelined processors.

[BibT_eX]

[DOI]

Martino Sykora

Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

Robust optimization of SoC architectures: A multi-scenario approach.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008

Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

A Modular Approach to Model Heterogeneous MPSoC at Cycle Level.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

A security monitoring service for NoCs.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

Efficiency and scalability of barrier synchronization on NoC based many-core architectures.

[BibT_eX]

[DOI]

Oreste Villa

Proceedings of the 2008 International Conference on Compilers, 2008

2007

Multi-Accuracy Power and Performance Transaction-Level Modeling.

[BibT_eX]

[DOI]

Giovanni Beltrame

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Exploration of distributed shared memory architectures for NoC-based multiprocessors.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

Efficient architecture/compiler co-exploration using analytical models.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2007

A topology design customization approach for STNoC.

[BibT_eX]

[DOI]

Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Application-Specific Topology Design Customization for STNoC.

[BibT_eX]

[DOI]

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations.

[BibT_eX]

[DOI]

Mariagiovanna Sami

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

A data protection unit for NoC-based architectures.

[BibT_eX]

[DOI]

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Mapping and Topology Customization Approaches for Application-Specific STNoC Designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006

Efficient Synchronization for Embedded On-Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

An efficient synchronization technique for multiprocessor systems on-chip.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2006

An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2006, 2006

A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures.

[BibT_eX]

[DOI]

Giovanni Beltrame

Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Power/performance hardware optimization for synchronization intensive applications in MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Exploiting TLM and object introspection for system-level simulation.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Decision-theoretic exploration of multiProcessor platforms.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005

Multi-objective design space exploration of embedded systems.

[BibT_eX]

[DOI]

J. Embed. Comput., 2005

Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach.

[BibT_eX]

[DOI]

Integr., 2005

Reducing the complexity of instruction-level power models for VLIW processors.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2005

2004

Multi-objective co-exploration of source code transformations and design space architectures for low-power embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2004

Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Compilers, 2004

2003

A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003

A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

A system-level methodology for fast multi-objective design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Branch prediction techniques for low-power VLIW processors.

[BibT_eX]

[DOI]

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

2002

Low-power data forwarding for VLIW embedded architectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

An instruction-level energy model for embedded VLIW architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2002

A Framework for Modeling and Estimating the Energy Dissipation of VLIW-Based Embedded Systems.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2002

An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Energy estimation and optimization of embedded VLIW processors based on instruction clustering.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

2001

Fast system-level exploration of memory architectures driven by energy-delay metrics.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Exploiting data forwarding to reduce the power budget of VLIW embedded processors.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

A design framework to efficiently explore energy-delay tradeoffs.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000

Low-power state assignment techniques for finite state machines.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Power Exploration for Embedded VLIW Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Instruction-level power estimation for embedded VLIW cores.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

Power optimization of system-level address buses based on software profiling.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999

Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study.

[BibT_eX]

[DOI]

William Fornaciari

Proceedings of the IEEE International Conference On Computer Design, 1999

Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems.

[BibT_eX]

[DOI]

William Fornaciari

Proceedings of the 1999 Design, 1999

Power estimation for architectural exploration of HW/SW communication on system-level buses.

[BibT_eX]

[DOI]

William Fornaciari

Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998

Automatic generation of error control codes for computer applications.

[BibT_eX]

[DOI]

Franco Fummi

IEEE Trans. Very Large Scale Integr. Syst., 1998

Power estimation of embedded systems: a hardware/software codesign approach.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1998

Power invariant vector compaction based on bit clustering and temporal partitioning.

[BibT_eX]

[DOI]

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Systematic AUED Codes for Self-Checking Architectures.

[BibT_eX]

[DOI]

Renato Stefanelli

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Address Bus Encoding Techniques for System-Level Power Optimization.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

1997

A VHDL-based approach for power estimation of embedded systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 1997

Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1995

Construction techniques for systematic SEC-DED codes with single byte error detection and partial correction capability for computer memory systems.

[BibT_eX]

[DOI]

Luca Penzo

IEEE Trans. Inf. Theory, 1995

VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes.

[BibT_eX]

[DOI]

Luca Penzo

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

GECO: A Tool for Automatic Generation of Error Control Codes for Computer Applications.

[BibT_eX]

Luca Penzo