Cristina Meinhardt

Fabian L. Cabrera

Proceedings of the Symposium on Internet of Things, 2024

Impact on Delay, Power and Area of Machine Learning-based Approximate Logic Synthesis.

[BibT_eX]

[DOI]

João Carlos Prats Ramos

Naiara Sachetti

Jônata Tyska Carvalho

Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

A Dual-Kernel Size-Configurable Gaussian Filter Architecture.

[BibT_eX]

[DOI]

Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

CeConP: Exploring Node Centrality for Early Routing Congestion Prediction.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

2023

New Modified 4:2 Approximate Compressors for Low-Power Applications.

[BibT_eX]

[DOI]

Vinicius Zanandrea

Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

A Detailed Electrical Analysis of SEE on 28 nm FDSOI SRAM Architectures.

[BibT_eX]

[DOI]

Frédéric Wrobel

Walter E. Calienes Bartra

Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

Impact on Radiation Robustness of Gate Mapping in FinFET Circuits under Work-function Fluctuation.

[BibT_eX]

[DOI]

Bernardo Borges Sandoval

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Fast and Low-Error Prediction of Logic Gate Cell Characterization.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

Adaptive Batch Size CGP: Improving Accuracy and Runtime for CGP Logic Optimization Flow.

[BibT_eX]

[DOI]

Bryan Martins Lima

Naiara Sachetti

Jônata Tyska Carvalho

Proceedings of the Genetic Programming - 26th European Conference, 2023

2022

Exploring XOR-based Full Adders and decoupling cells to variability mitigation at FinFET technology.

[BibT_eX]

[DOI]

Integr., 2022

Optimizing machine learning logic circuits with constant signal propagation.

[BibT_eX]

[DOI]

André Inácio Reis

Integr., 2022

Accuracy-Configurable 2-D Gaussian Filter Architecture for Energy-Efficient Image Processing.

[BibT_eX]

[DOI]

Talita Alves Borges

Vagner Santos Da Rosa

IEEE Des. Test, 2022

Exploring Approximate Computing Approaches to Design Power-efficient Multipliers.

[BibT_eX]

[DOI]

Vinicius Zanandrea

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Approximation Workflow for Energy-Efficient Comparators in Decision Tree Applications.

[BibT_eX]

[DOI]

Pedro Aquino Silva

Mateus Grellert

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Exploring Approximate Comparator Circuits on Power Efficient Design of Decision Trees.

[BibT_eX]

[DOI]

Pedro Aquino Silva

Mateus Grellert

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Routability-Driven Detailed Placement Using Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing.

[BibT_eX]

[DOI]

Rafael B. Schvittz

Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

Exploring Machine Learning for Electrical Behavior Prediction: The CMOS Inverter Case Study.

[BibT_eX]

[DOI]

Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

An architecture proposal for checkpoint/restore on stateful containers.

[BibT_eX]

[DOI]

Rodrigo H. Müller

Odorico M. Mendizabal

Proceedings of the SAC '22: The 37th ACM/SIGAPP Symposium on Applied Computing, Virtual Event, April 25, 2022

Exploring the Impacts of Multiple Kernel Sizes of Gaussian Filters Combined to Approximate Computing in Canny Edge Detection.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

E-RVP: An Initial Design Rule Violation Predictor Using Placement Information.

[BibT_eX]

[DOI]

Sheiny Fabre Almeida

Aysa Fakheri Tabrizi

Erfan Aghaeekiasaraee

Renan Netto

Tiago Augusto Fontana

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021

Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions.

[BibT_eX]

[DOI]

Luiz Gustavo Coutinho Xavier

Paulo Francisco Butzen

J. Electron. Test., 2021

Shrinking Logs by Safely Discarding Commands.

[BibT_eX]

[DOI]

Fernando Luís Dotti

Odorico M. Mendizabal

Proceedings of the 39th Brazilian Symposium on Computer Networks and Distributed Systems, 2021

Exploring Gate Mapping and Transistor Sizing to Improve Radiation Robustness: A C17 Benchmark Case-study.

[BibT_eX]

[DOI]

Bernardo Borges Sandoval

Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

SET Mitigation Techniques on Mirror Full Adder at 7 nm FinFET Technology.

[BibT_eX]

[DOI]

Maria Eduarda de Melo Hang

Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

Current Behavior on Process Variability Aware FinFET Inverter Designs.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Soft Error Sensibility Window at FinFET DICE SRAM.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Design of Energy-Efficient Gaussian Filters by Combining Refactoring and Approximate Adders.

[BibT_eX]

[DOI]

José Luís Güntzel

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Fast Logic Optimization Using Decision Trees.

[BibT_eX]

[DOI]

Brunno A. Abreu

Isac de Souza Campos

Jônata Tyska Carvalho

Mateus Grellert

Sergio Bampi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Multi-Level Design Influences on Robustness Evaluation of 7nm FinFET Technology.

[BibT_eX]

[DOI]

Luiz Gustavo Coutinho Xavier

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Scalable and Decoupled Logging for State Machine Replication.

[BibT_eX]

[DOI]

Fernando Luís Dotti

Odorico Machado Mendizabal

Proceedings of the XXXVIII Brazilian Symposium on Computer Networks and Distributed Systems, 2020

A Fine-grained Methodology for Accuracy-configurable and Energy-efficient Gaussian Filters Design.

[BibT_eX]

[DOI]

Talita Alves Borges

Fabio G. Rossato G. da Silva

Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Mitigation Effects of Decoupling Cells on Full Adders Process Variability.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Circuit Level Design Methods to Mitigate Soft Errors.

[BibT_eX]

[DOI]

Proceedings of the IEEE Latin-American Test Symposium, 2020

Soft Error Reliability of SRAM cells during the three operation states.

[BibT_eX]

[DOI]

Proceedings of the IEEE Latin-American Test Symposium, 2020

Work-Function Fluctuation Impact on the SET Response of FinFET-based Majority Voters.

[BibT_eX]

[DOI]

Proceedings of the IEEE Latin-American Test Symposium, 2020

Pros and Cons of ST and SIG FinFET Inverters for Low Power Designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Energy-Efficient Design of Approximated Full Adders.

[BibT_eX]

[DOI]

Pedro Aquino Silva

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Mirror Full Adder SET Susceptibility on 7nm FinFET Technology.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019

Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs.

[BibT_eX]

[DOI]

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Robust FinFET Schmitt Trigger Designs for Low Power Applications.

[BibT_eX]

[DOI]

Alexandra Lackmann Zimpeck

Proceedings of the VLSI-SoC: New Technology Enabler, 2019

Robustness and Minimum Energy-Oriented FinFET Design.

[BibT_eX]

[DOI]

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability.

[BibT_eX]

[DOI]

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Impact of Process Variability and Single Event Transient on FinFET Technology.

[BibT_eX]

[DOI]

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Evaluation of SET under Process Variability on FinFET Multi-level Design.

[BibT_eX]

[DOI]

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Process Variability Impact on the SET Response of FinFET Multi-level Design.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: New Technology Enabler, 2019

A library for services transparent replication.

[BibT_eX]

[DOI]

Paola Martins Pereira

Fernando Luís Dotti

Odorico Machado Mendizabal

Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, 2019

Exploring Schmitt Trigger Circuits for Process Variability Mitigation.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Process Variability Challenges for Radiation Mitigation Techniques on 16nm.

[BibT_eX]

[DOI]

Samuel Presa Toledo

Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

Sleep Transistors to Improve the Process Variability and Soft Error Susceptibility.

[BibT_eX]

[DOI]

Fabio G. Rossato G. da Silva

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

FinFET Variability and Near-threshold operation: Impact on Full Adders design using XOR Blocks.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Radiation Effects in XOR Logic Gates at 16nm CMOS and FinFET Technology.

[BibT_eX]

[DOI]

Alan D. Lüdke

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

FBM: A Simple and Fast Algorithm for Placement Legalization.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018

Impact of different transistor arrangements on gate variability.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

Evaluation of variability using Schmitt trigger on full adders layout.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies.

[BibT_eX]

[DOI]

Roberto B. Almeida

Microelectron. Reliab., 2018

Evaluating the Impact of Process Variability and Radiation Effects on Different Transistor Arrangements.

[BibT_eX]

[DOI]

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

16NM 6T and 8T CMOS SRAM Cell Robustness Against Process Variability and Aging Effects.

[BibT_eX]

[DOI]

Roberto B. Almeida

Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Reliability evaluation of circuits designed in multi- and single-stage versions.

[BibT_eX]

[DOI]

Rafael B. Schvittz

Matheus F. Pontes

Denis Teixeira Franco

Lirida A. B. Naviner

Leomar S. da Rosa

Fabio G. Rossato G. da Silva

Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Pros and Cons of Schmitt Trigger Inverters to Mitigate PVT Variability on Full Adders.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Impact of Near-Threshold and Variability on 7nm FinFET XOR Circuits.

[BibT_eX]

[DOI]

Nelson de Farias Traversi

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Exploring MAS to a High Level Abstration NoC Simulation Environment.

[BibT_eX]

[DOI]

Gustavo L. Lima

Diana Francisca Adamatti

Graçaliz Pereira Dimuro

Odorico Machado Mendizabal

Eduardo Wenzel Brião

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Exploring Multi-level Design to Mitigate Variability and Radiation Effects on 7nm FinFET Logic Cells.

[BibT_eX]

[DOI]

Walter E. Calienes Bartra

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017

Evaluation of heavy-ion impact in bulk and FDSOI devices under ZTC condition.

[BibT_eX]

[DOI]

Y. Q. de Aguiar

Andrei Vladimirescu

Microelectron. Reliab., 2017

Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2017

Radiation sensitivity of XOR topologies in multigate technologies under voltage variability.

[BibT_eX]

[DOI]

Ygor Q. de Aguiar

Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Robustness of Sub-22nm multigate devices against physical variability.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Comparing 32nm full adder TMR and DTMR architectures.

[BibT_eX]

[DOI]

Giane Ulloa

Vinicius Lucena

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Impact of schmitt trigger inverters on process variability robustness of 1-Bit full adders.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Temperature dependence and ZTC bias point evaluation of sub 20nm bulk multigate devices.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

SET response of FinFET-based majority voter circuits under work-function fluctuation.

[BibT_eX]

[DOI]

Y. Q. de Aguiar

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016

Permanent and single event transient faults reliability evaluation EDA tool.

[BibT_eX]

[DOI]

Y. Q. de Aguiar

Microelectron. Reliab., 2016

Inserting permanent fault input dependence on PTM to improve robustness evaluation.

[BibT_eX]

[DOI]

Rafael B. Schivittz

Rafael Fritz

Denis Teixeira Franco

Lirida A. B. Naviner

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Investigating PVT variability effects on full adders.

[BibT_eX]

[DOI]

Stephanie O. Ames

Vinicius Zanandrea

Ingrid F. V. Oliveira

Samuel P. Toledo

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

A probabilistic model for stuck-on faults in combinational logic gates.

[BibT_eX]

[DOI]

Rafael B. Schivittz

Denis Teixeira Franco

Proceedings of the 17th Latin-American Test Symposium, 2016

Reliability analysis of majority voters under permanent faults.

[BibT_eX]

[DOI]

Eduardo Liebl

Proceedings of the 17th Latin-American Test Symposium, 2016

FinFET cells with different transistor sizing techniques against PVT variations.

[BibT_eX]

[DOI]

Gracieli Posser

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Geometric variability impact on 7nm Trigate combinational cells.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

PVT variability analysis of FinFET and CMOS XOR circuits at 16nm.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015

Impact of PVT variability on 20 nm FinFET standard cells.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2015

Process variability in FinFET standard cells with different transistor sizing techniques.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

An evaluation of BTI degradation of 32nm standard cells.

[BibT_eX]

[DOI]

Rafael B. Schivittz

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014

Predictive evaluation of electrical characteristics of sub-22 nm FinFET technologies under device geometry variations.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2014

Evaluating the impact of environment and physical variability on the ION current of 20nm FinFET devices.

[BibT_eX]

[DOI]

Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Exploring more efficient architectures for Multiple Dynamic Supply Voltage designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Comparing high-performance cells in CMOS bulk and FinFET technologies.

[BibT_eX]

[DOI]

Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices.

[BibT_eX]

[DOI]

Gracieli Posser

Jozeanne Belomo

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Impact of gate workfunction fluctuation on FinFET standard cells.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013

FinFET basic cells evaluation for regular layouts.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

A yield-driven regular layout synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

A novel approach to reduce power consumption in level shifter for Multiple Dynamic Supply Voltage.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Electronics, 2013

2011

A Low-Cost Solution for Deploying Processor Cores in Harsh Environments.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., 2011

2009

Recovery scheme for hardening system on programmable chips.

[BibT_eX]

[DOI]

Proceedings of the 10th Latin American Test Workshop, 2009

An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2007

Logic and Physical Synthesis of Cell Arrays.

[BibT_eX]

[DOI]

Reginaldo Tavares

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

A Regular Layout Approach for ASICs.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

orBDDs Direct Mapping for Structured Logic Circuits.

[BibT_eX]

[DOI]

Reginaldo Tavares