Cristiana Bolchini
Orcid: 0000-0001-5065-7906Affiliations:
- Politecnico di Milano, Italy
According to our database1,
Cristiana Bolchini
authored at least 147 papers
between 1993 and 2024.
Collaborative distances:
Collaborative distances:
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Online presence:
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on zbmath.org
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on orcid.org
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on dl.acm.org
On csauthors.net:
Bibliography
2024
Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space.
Proceedings of the IEEE European Test Symposium, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
IEEE Trans. Computers, April, 2023
Resilience of Deep Learning applications: a systematic survey of analysis and hardening techniques.
CoRR, 2023
Analyzing the Reliability of Alternative Convolution Implementations for Deep Learning Applications.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
2022
A Runtime Resource Management and Provisioning Middleware for Fog Computing Infrastructures.
ACM Trans. Internet Things, 2022
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Computers, 2022
IEEE Des. Test, 2022
Recommending Relevant Papers to Conference Participants: a Deep Learning Driven Content-based Approach.
Proceedings of the UMAP '22: 30th ACM Conference on User Modeling, Adaptation and Personalization, Barcelona, Spain, July 4, 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
IEEE Trans. Computers, 2020
IEEE Des. Test, 2020
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
2019
Scalable analytical model for reliability measures in aging VLSI by interacting Markovian agents.
Perform. Evaluation, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
A Runtime Resource Management Policy for OpenCL Workloads on Heterogeneous Multicores.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
SIGBED Rev., 2018
Approximation-aware coordinated power/performance management for heterogeneous multi-cores.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
A Fully Automated and Configurable Cost-Aware Framework for Adaptive Functional Diagnosis.
IEEE Des. Test, 2017
Scalable analytical model of the reliability of multi-core systems-on-chip by interacting Markovian agents.
Proceedings of the 11th EAI International Conference on Performance Evaluation Methodologies and Tools, 2017
Epistemic uncertainty propagation in a Weibull environment for a two-core system-on-chip.
Proceedings of the 2nd International Conference on System Reliability and Safety, 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
2016
Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.
IEEE Trans. Computers, 2016
IEEE Trans. Computers, 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Using just-in-time code generation for transparent resource management in heterogeneous systems.
Proceedings of the 2nd IEEE International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow, 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
A self-adaptive approach to efficiently manage energy and performance in tomorrow's heterogeneous computing systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Lifetime-aware load distribution policies in multi-core systems: An in-depth analysis.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
An Expert CAD Flow for Incremental Functional Diagnosis of Complex Electronic Boards.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Des. Test, 2015
An orchestrated approach to efficiently manage resources in heterogeneous system architectures.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
A System-Level Simulation Framework for Evaluating Resource Management Policies for Heterogeneous System Architectures.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
A configurable board-level adaptive incremental diagnosis technique based on decision trees.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
2014
ACM Trans. Design Autom. Electr. Syst., 2014
Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014
A lightweight and open-source framework for the lifetime estimation of multicore systems.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
Machine learning-based techniques for incremental functional diagnosis: A comparative analysis.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
Combined DVFS and mapping exploration for lifetime and soft-error susceptibility improvement in MPSoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014
2013
IEEE Trans. Computers, 2013
Inf. Syst., 2013
J. Electron. Test., 2013
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Analysis and comparison of functional verification and ATPG for testing design reliability.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
2012
Proceedings of the Methodologies and Technologies for Networked Enterprises, 2012
Proceedings of the Methodologies and Technologies for Networked Enterprises, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
A Novel Design Methodology for Implementing Reliability-Aware Systems on SRAM-Based FPGAs.
IEEE Trans. Computers, 2011
The ESTEEM platform: enabling P2P semantic collaboration through emerging collective knowledge.
J. Intell. Inf. Syst., 2011
IEEE Data Eng. Bull., 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Combined architecture and hardening techniques exploration for reliable embedded system design.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
2010
Emergent Semantics and Cooperation in Multi-knowledge Communities: the ESTEEM Approach.
World Wide Web, 2010
Guest Editors' Introduction: Special Section on System-Level Design of Reliable Architectures.
IEEE Trans. Computers, 2010
Fault Classification for SRAM-Based FPGAs in the Space Environment for Fault Mitigation.
IEEE Embed. Syst. Lett., 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA Platforms.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
A multi-objective genetic algorithm framework for design space exploration of reliable FPGA-based systems.
Proceedings of the IEEE Congress on Evolutionary Computation, 2010
2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-Based FPGA Systems.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
2008
J. Electron. Test., 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space exploration.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Proceedings of the 8th International Conference on Mobile Data Management (MDM 2007), 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Exploring Partial Reconfiguration for Mitigating SEU faults in SRAM-Based FPGAs.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007
Proceedings of the Conceptual Modeling, 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Proceedings of the Modeling and Using Context, 2007
2006
J. Syst. Archit., 2006
Context integration for mobile data tailoring.
Proceedings of the Fourteenth Italian Symposium on Advanced Database Systems, 2006
Proceedings of the On the Move to Meaningful Internet Systems 2006: OTM 2006 Workshops, 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 2005 Design, 2005
Proceedings of the IEEE Congress on Evolutionary Computation, 2005
2004
PoLiDBMS: Design and Prototype Implementation of a DBMS for Portable Devices.
Proceedings of the Twelfth Italian Symposium on Advanced Database Systems, 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
2003
IEEE Trans. Reliab., 2003
ACM Trans. Inf. Syst., 2003
IEEE Trans. Instrum. Meas., 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
2002
J. Electron. Test., 2002
Smart card embedded information systems: a methodology for privacy oriented architectural design.
Data Knowl. Eng., 2002
Physical and Logical Data Structures for Very Small Databases.
Proceedings of the Decimo Convegno Nazionale su Sistemi Evoluti per Basi di Dati, 2002
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
2001
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
2000
Design of VHDL-based totally self-checking finite-state machine and data-path descriptions.
IEEE Trans. Very Large Scale Integr. Syst., 2000
1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
1998
IEEE Des. Test Comput., 1998
Proceedings of the 11th International Symposium on System Synthesis, 1998
Proceedings of the 1998 Design, 1998
1997
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
Proceedings of the European Design and Test Conference, 1997
1996
Proceedings of the conference on European design automation, 1996
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
1995
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
A BDD Based Algorithm for Detecting Difficult Faults.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995
1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
A CMOS Fault Tolerant Architecture for Swith-Level Faults.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994
1993
Microprocess. Microprogramming, 1993