Cristell Maneux

Orcid: 0000-0001-9125-5372

According to our database1, Cristell Maneux authored at least 44 papers between 2003 and 2024.

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Bibliography

2024

2023
InP DHBT Analytical Modeling: Toward THz Transistors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

SPICE Modeling in Verilog-A for Photo-Response in UTC-Photodiodes Targeting Beyond-5G Circuit Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

Electrothermal modeling of junctionless vertical Si nanowire transistors for 3D logic circuit design.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022
Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

A Logic Cell Design and routing Methodology Specific to VNWFET.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

InP DHBT test structure optimization towards 110 GHz characterization.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022

2021
Impact of Hot Carrier Degradation on the Performances of Current Mirrors based on a 55 nm BiCMOS Integrated Circuit Technology.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

Ultra Compact High responsivity Photodiodes for >100 Gbaud Applications.
Proceedings of the European Conference on Optical Communication, 2021

Electro-Thermal Limitations and Device Degradation of SiGe HBTs with Emphasis on Circuit Performance.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2021

InP DHBT Characterization up to 500 GHz and Compact Model Validation Towards THz Circuit Design.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2021

0.4-μm InP/InGaAs DHBT with a 380-GHz ${f_{T}}$, > 600-GHz $f_{\max}$ and BVCE0 > 4.5 V.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2021

Investigation of 0.18μm CMOS Sensitivity to BTI and HCI Mechanisms under Extreme Thermal Stress Conditions.
Proceedings of the 30th IEEE Asian Test Symposium, 2021

2020
3D logic cells design and results based on Vertical NWFET technology including tied compact model.
CoRR, 2020

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.
Proceedings of the VLSI-SoC: Design Trends, 2020

2019
First Uni-Traveling Carrier Photodiode Compact Model Enabling Future Terahertz Communication System Design.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

Impact of SiGe HBT hot-carrier degradation on the broadband amplifier output supply current.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

Measurement based accurate definition of the SOA edges for SiGe HBTs.
Proceedings of the 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019

2018
Multiscaled Simulation Methodology for Neuro-Inspired Circuits Demonstrated with an Organic Memristor.
IEEE Trans. Multi Scale Comput. Syst., 2018

2017
Si/SiGe: C and InP/GaAsSb Heterojunction Bipolar Transistors for THz Applications.
Proc. IEEE, 2017

Random telegraph noise in SiGe HBTs: Reliability analysis close to SOA limit.
Microelectron. Reliab., 2017

1/f Noise in 3D vertical gate-all-around junction-less silicon nanowire transistors.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

Avalanche compact model featuring SiGe HBTs characteristics up to BVcbo.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016
Comprehensive study of random telegraph noise in base and collector of advanced SiGe HBT: Bias, geometry and trap locations.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

Physics-based electrical compact model for monolayer Graphene FETs.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015
Reliability of high-speed SiGe: C HBT under electrical stress close to the SOA limit.
Microelectron. Reliab., 2015

Substrate-coupling effect in BiCMOS technology for millimeter wave applications.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Graphene FET evaluation for RF and mmWave circuit applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Characterization and modeling of low-frequency noise in CVD-grown graphene FETs.
Proceedings of the 45th European Solid State Device Research Conference, 2015

A new physics-based compact model for Bilayer Graphene Field-Effect Transistors.
Proceedings of the 45th European Solid State Device Research Conference, 2015

2014
Qualitative assessment of epitaxial graphene FETs on SiC substrates via pulsed measurements and temperature variation.
Proceedings of the 44th European Solid State Device Research Conference, 2014

2012
Pulsed I(V) - pulsed RF measurement system for microwave device characterization with 80ns/45GHz.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

Advancements on reliability-aware analog circuit design.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
Design and Modeling of a Neuro-Inspired Learning Circuit Using Nanotube-Based Memory Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Reliability of submicron InGaAs/InP DHBT under thermal and electrical stresses.
Microelectron. Reliab., 2011

Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design.
Microelectron. Reliab., 2011

2010
Preliminary results of storage accelerated aging test on InP/InGaAs DHBT.
Microelectron. Reliab., 2010

Thermal aging model of InP/InGaAs/InP DHBT.
Microelectron. Reliab., 2010

From nanoscale technology scenarios to compact device models for ambipolar devices.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2007
CNTFET Modeling and Reconfigurable Logic-Circuit Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

2004
Low frequency noise as a reliability diagnostic tool in compound semiconductor transistors.
Microelectron. Reliab., 2004

On-wafer low frequency noise measurements of SiGe HBTs: Impact of technological improvements on 1/f noise.
Microelectron. Reliab., 2004

2003
1/f noise analysis of InP/InGaAs DHBTs submitted to bias and thermal stresses.
Microelectron. Reliab., 2003

High current effects in InP/GaAsSb/InP DHBT: Physical mechanisms and parasitic effects.
Microelectron. Reliab., 2003


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