Crispín Gómez Requena
According to our database1,
Crispín Gómez Requena
authored at least 33 papers
between 2007 and 2019.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2019
Combining Source-adaptive and Oblivious Routing with Congestion Control in High-performance Interconnects using Hybrid and Direct Topologies.
ACM Trans. Archit. Code Optim., 2019
2018
J. Parallel Distributed Comput., 2018
2017
Parallel Comput., 2017
2016
IEEE Trans. Parallel Distributed Syst., 2016
The k-ary n-direct s-indirect family of topologies for large-scale interconnection networks.
J. Supercomput., 2016
Proceedings of the 24th Euromicro International Conference on Parallel, 2016
2015
J. Supercomput., 2015
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015
Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015
2014
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014
Combining HoL-blocking avoidance and differentiated services in high-speed interconnects.
Proceedings of the 21st International Conference on High Performance Computing, 2014
2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
Proceedings of the International Conference on Computational Science, 2013
BBQ: A Straightforward Queuing Scheme to Reduce HoL-Blocking in High-Performance Hybrid Networks.
Proceedings of the Euro-Par 2013 Parallel Processing, 2013
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013
2012
Proceedings of the 11th IEEE International Symposium on Network Computing and Applications, 2012
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012
2011
Concurr. Comput. Pract. Exp., 2011
Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture.
Proceedings of the Design, Automation and Test in Europe, 2011
2009
FT<sup>2</sup>EI: A Dynamic Fault-Tolerant Routing Methodology for Fat Trees with Exclusion Intervals.
IEEE Trans. Parallel Distributed Syst., 2009
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Comput. Archit. Lett., 2008
Proceedings of the 16th Euromicro International Conference on Parallel, 2008
Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008
Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008
2007
An Efficient Fault-Tolerant Routing Methodology for Fat-Tree Interconnection Networks.
Proceedings of the Parallel and Distributed Processing and Applications, 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007