Crescenzo D'Alessandro

According to our database1, Crescenzo D'Alessandro authored at least 12 papers between 2005 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2009
Phase-encoding : an event based scheme for on-chip signalling.
PhD thesis, 2009

Synthesis of Multiple Rail Phase Encoding Circuits.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

2008
Phase-Encoding for On-Chip Signalling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Global interconnections in FPGAs: modeling and performance analysis.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Implementation of Wave-Pipelined Interconnects in FPGAs.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Implementation of a phase-encoding signalling prototype chip.
Proceedings of the ESSCIRC 2008, 2008

Serialized Asynchronous Links for NoC.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Reducing Interconnect Cost in NoC through Serialized Asynchronous Links.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

NoC Communication Strategies Using Time-to-Digital Conversion.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Delay/Phase Regeneration Circuits.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

2006
Multiple-Rail Phase-Encoding for NoC.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2005
PSK Signalling on NoC Buses.
Proceedings of the Integrated Circuit and System Design, 2005


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