Craig R. Walters

Orcid: 0000-0002-3973-8155

According to our database1, Craig R. Walters authored at least 10 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

2010
2012
2014
2016
2018
2020
2022
2024
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Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
IBM z16 Modular Scalable Cache Hierarchy and Future Concept Applications.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Enterprise-Class Cache Compression Design.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
Enterprise-Class Multilevel Cache Design: Low Latency, Huge Capacity, and High Reliability.
IEEE Micro, 2023

2020
Design of the IBM z15 microprocessor.
IBM J. Res. Dev., 2020

2018
Performance innovations in the IBM z14 platform.
IBM J. Res. Dev., 2018

2015
The IBM z13 processor cache subsystem.
IBM J. Res. Dev., 2015

2012
Performance innovation in the IBM zEnterprise 196 processor.
IBM J. Res. Dev., 2012

IBM zEnterprise 196 microprocessor and cache subsystem.
IBM J. Res. Dev., 2012

2009
IBM System z10 processor cache subsystem microarchitecture.
IBM J. Res. Dev., 2009

IBM System z10 I/O subsystem.
IBM J. Res. Dev., 2009


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