Cong-Kha Pham

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding.

[BibT_eX]

[DOI]

Proceedings of the Computational Science and Its Applications - ICCSA 2024 Workshops, 2024

RISC-V-Based System-on-Chips for IoT Applications.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE Hot Chips Symposium, 2024

A Trusted Execution Environment RISC-V System on Chip.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE Hot Chips Symposium, 2024

2023

Transition Factors of Power Consumption Models for CPA Attacks on Cryptographic RISC-V SoC.

[BibT_eX]

[DOI]

IEEE Trans. Computers, September, 2023

A High-Efficiency Modular Multiplication Digital Signal Processing for Lattice-Based Post-Quantum Cryptography.

[BibT_eX]

[DOI]

Trong-Hung Nguyen

Cryptogr., September, 2023

A flexible and efficient FPGA-based random forest architecture for IoT applications.

[BibT_eX]

[DOI]

Internet Things, July, 2023

A Survey of Post-Quantum Cryptography: Start of a New Race.

[BibT_eX]

[DOI]

Cryptogr., July, 2023

On the performance of non-profiled side channel attacks based on deep learning techniques.

[BibT_eX]

[DOI]

IET Inf. Secur., May, 2023

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA.

[BibT_eX]

[DOI]

Future Internet, May, 2023

A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment.

[BibT_eX]

[DOI]

Comput. Electr. Eng., January, 2023

Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process.

[BibT_eX]

[DOI]

Hong-Hai Thai

Sensors, 2023

Multi-Functional Resource-Constrained Elliptic Curve Cryptographic Processor.

[BibT_eX]

[DOI]

IEEE Access, 2023

FPGA-Based Secured and Efficient Lightweight IoT Edge Devices with Customized RISC-V.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computing and Communication Technologies, 2023

Revealing Secret Key from Low Success Rate Deep Learning-Based Side Channel Attacks.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

In-NVRAM Unified PUF and TRNG Based on Standard CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Unified PUF and Crypto Core Exploiting the Metastability in Latches.

[BibT_eX]

[DOI]

Future Internet, 2022

ChaCha20-Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3.

[BibT_eX]

[DOI]

Cryptogr., 2022

Low-Cost Area-Efficient FPGA-Based Multi-Functional ECDSA/EdDSA.

[BibT_eX]

[DOI]

Cryptogr., 2022

A Unified NVRAM and TRNG in Standard CMOS Technology.

[BibT_eX]

[DOI]

IEEE Access, 2022

A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse.

[BibT_eX]

[DOI]

IEEE Access, 2022

Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling.

[BibT_eX]

[DOI]

IEEE Access, 2022

Low Complexity Correlation Power Analysis by Combining Power Trace Biasing and Correlation Distribution Techniques.

[BibT_eX]

[DOI]

Ngoc-Tuan Do

IEEE Access, 2022

High-performance Multi-function HMAC-SHA2 FPGA Implementation.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

A Novel Ring Oscillator PUF for FPGA Based on Feedforward Ring Oscillators.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

Spectre attack detection with Neutral Network on RISC-V processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

High-speed FPGA-based Design and Implementation of Text Search Processor.

[BibT_eX]

[DOI]

Proceedings of the International Conference on IC Design and Technology, 2022

A System-on-Chip for IoT Applications with 16-bit Tiny Processor.

[BibT_eX]

[DOI]

Tuan-Kiet Dang

Khai-Duy Nguyen

Proceedings of the International Conference on IC Design and Technology, 2022

A Combined Blinding-Shuffling Online Template Attacks Countermeasure Based on Randomized Domain Montgomery Multiplication.

[BibT_eX]

[DOI]

Bien-Cuong Nguyen

Proceedings of the IEEE International Conference on Consumer Electronics, 2022

2021

A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Convergence of 5G Technologies, Artificial Intelligence and Cybersecurity of Networked Societies for the Cities of Tomorrow.

[BibT_eX]

[DOI]

Trung Q. Duong

Mob. Networks Appl., 2021

A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction.

[BibT_eX]

[DOI]

Khai-Duy Nguyen

Tuan-Kiet Dang

Xuan-Tu Tran

IEICE Electron. Express, 2021

A proposal for enhancing training speed in deep learning models based on memory activity survey.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2021

A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse.

[BibT_eX]

[DOI]

IEEE Access, 2021

A Real-Time Cache Side-Channel Attack Detection System on RISC-V Out-of-Order Processor.

[BibT_eX]

[DOI]

IEEE Access, 2021

Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure.

[BibT_eX]

[DOI]

IEEE Access, 2021

Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks.

[BibT_eX]

[DOI]

IEEE Access, 2021

A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip.

[BibT_eX]

[DOI]

Khai-Duy Nguyen

Tuan-Kiet Dang

Proceedings of the IEEE Hot Chips 33 Symposium, 2021

System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2020

A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2020

Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Errors in Stationary Blocks.

[BibT_eX]

[DOI]

EAI Endorsed Trans. Ind. Networks Intell. Syst., 2020

Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB).

[BibT_eX]

[DOI]

IEICE Electron. Express, 2020

Quick Boot of Trusted Execution Environment With Hardware Accelerators.

[BibT_eX]

[DOI]

Ckristian Duran

Duc-Thinh Nguyen-Hoang

IEEE Access, 2020

Heterogeneous Hardware-assisted Parallel Processing for BWA-MEM DNA Alignment.

[BibT_eX]

[DOI]

Binh Kieu-Do-Nguyen

Cuong Pham-Quoc

Proceedings of the 2020 RIVF International Conference on Computing and Communication Technologies, 2020

Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Hardware-assisted High-performance DNA Alignment System.

[BibT_eX]

[DOI]

Binh Kieu-Do-Nguyen

Cuong Pham-Quoc

Proceedings of the ICIIT 2020: 5th International Conference on Intelligent Information Technology, 2020

2019

An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 1.2-V 162.9 pJ/cycle bitmap index creation core with 0.31-pW/bit standby power on 65-nm SOTB.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2019

A 1.05-V 62-MHz with 0.12-nW standby power SOTB-65 nm chip of 32-point DCT based on adaptive CORDIC.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2019

A 1.2-V 90-MHz Bitmap Index Creation Accelerator with 0.27-nW Standby Power on 65-nm Silicon-On-Thin-Box (SOTB) CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Live Demonstration: Real-Time Auto-Exposure Histogram Equalization Video-System using Frequent Items Counter.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 0.75-V 32-MHz 181-µW SOTB-65nm Floating-point Twiddle Factor Using Adaptive CORDIC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Industrial Technology, 2019

An Efficient Hardware Implementation of Radix-16 Montgomery Multiplication.

[BibT_eX]

[DOI]

Bien-Cuong Nguyen

Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

2018

A Low-Power Hybrid Adaptive CORDIC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

A High-Throughput Low-Energy Arithmetic Processor.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2018

A CORDIC-based QR decomposition for MIMO signal detector.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

Frequent items counter based on binary decoders.

[BibT_eX]

[DOI]

Katsumi Inoue

IEICE Electron. Express, 2018

Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation.

[BibT_eX]

[DOI]

IEEE Access, 2018

VLSI Design of Frequent Items Counting Using Binary Decoders Applied to 8-bit per Item Case-study.

[BibT_eX]

[DOI]

Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

VLSI Design of Floating-Point Twiddle Factor Using Adaptive CORDIC on Various Iteration Limitations.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

High-speed 8/16/32-point DCT Architecture Using Fixed-rotation Adaptive CORDIC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Hardware Implementation of Background Calibration Technique for TIADCs with Signals in Any Nyquist Bands.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

An efficient fixed-point arithmetic processor using a hybrid CORDIC algorithm.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Low-Latency Parallel Pipeline CORDIC.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2017

A Flexible High-Bandwidth Low-Latency Multi-Port Memory Controller.

[BibT_eX]

[DOI]

CoRR, 2017

FPGA-based frequent items counting using matrix of equality comparators.

[BibT_eX]

[DOI]

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A low power AES-GCM authenticated encryption core in 65nm SOTB CMOS process.

[BibT_eX]

[DOI]

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Reliable and energy-efficient transmission on the Internet-of-Video-Things.

[BibT_eX]

[DOI]

Yuichiro Mori

Proceedings of the 17th International Symposium on Communications and Information Technologies, 2017

Highly parallel bitmap-based regular expression matching for text analytics.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

An FPGA approach for high-performance multi-match priority encoder.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

An FPGA approach for fast bitmap indexing.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

A compact, ultra-low power AES-CCM IP core for wireless body area networks.

[BibT_eX]

[DOI]

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

An ultra-low power AES encryption core in 65nm SOTB CMOS process.

[BibT_eX]

[DOI]

Van-Lan Dao

Proceedings of the International SoC Design Conference, 2016

An efficient FPGA-based database processor for fast database analytics.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A hybrid adaptive CORDIC in 65nm SOTB CMOS process.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A high-throughput and low-power design for bitmap indexing on 65-nm SOTB CMOS process.

[BibT_eX]

[DOI]

Proceedings of the International Conference on IC Design and Technology, 2016

2015

A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2015

Low-resource low-latency hybrid adaptive CORDIC with floating-point precision.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

Design of co-processor for real-time HMM-based text-to-speech on hardware system applied to Vietnamese.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

Parallel pipelining configurable multi-port memory controller for multimedia applications.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

SAR: A Self-Adaptive and Reliable protocol for wireless multimedia sensor networks.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on Ubiquitous and Future Networks, 2015

Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

An efficient multi-port memory controller for multimedia applications.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

A CAM-Based Information Detection Hardware System for Fast Image Matching on FPGA.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2014

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

2013

Design a Fast CAM-Based Exact Pattern Matching System on FPGA and 0.18µm CMOS Process.

[BibT_eX]

[DOI]

Katsumi Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Low Complexity Logarithmic and Anti-Logarithmic Converters for Hybrid Number System Processors and DSP Applications.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A CAM-based Information Detection Hardware System for fast exact pattern matching.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A fast CAM-based image matching system on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A fast CAM-based Watermarking extraction on FPGA.

[BibT_eX]

[DOI]

Proceedings of 2013 International Conference on IC Design & Technology, 2013

2012

An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

An Improved Hybrid LUT-Based Architecture for Low-Error and Efficient Fixed-Width Squarer.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Efficient LUT-Based Truncated Multiplier and Its Application in RGB to YCbCr Color Space Conversion.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

2011

An Improved Linear Difference Method with High ROM Compression Ratio in Direct Digital Frequency Synthesizer.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

2010

A Low-Power High-PSRR Low-Dropout Regulator With Bulk-Gate Controlled Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A compact adaptive slope compensation circuit for Current-Mode DC-DC converter.

[BibT_eX]

[DOI]

Kimio Shibata

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A DC-DC Converter using a high speed soft-start control circuit.

[BibT_eX]

[DOI]

Kimio Shibata

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

A Low-Power High Accuracy Over Current Protection Circuit for Low Dropout Regulator.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2009

Low Power LDO with Fast Load Transient Response based on Quick Response Circuit.

[BibT_eX]

[DOI]

Weichun Tung

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2007

Compensated circuit for Low Dropout Regulator having stable load regulation after consideration of bonding wire resistance.

[BibT_eX]

[DOI]

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

An Edge Extraction Method for Color Image Using Multiple-Valued LoG Filter and Color Space.

[BibT_eX]

[DOI]

Koutaro Yamano

Proceedings of the 6th Annual IEEE/ACIS International Conference on Computer and Information Science (ICIS 2007), 2007

CMOS Schmitt Trigger Circuit with Controllable Hysteresis Using Logical Threshold Voltage Control Circuit.

[BibT_eX]

[DOI]

Proceedings of the 6th Annual IEEE/ACIS International Conference on Computer and Information Science (ICIS 2007), 2007

2006

A Proposal to Solve N-Queens Problems Using Maximum Neuron Model with A Modified Hill-Climbing Term.

[BibT_eX]

[DOI]

Wataru Noguchi

Proceedings of the International Joint Conference on Neural Networks, 2006

Simple Logic Threshold Conversion Circuits.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

A hardware accelerator for solving the n-queen problem.

[BibT_eX]

Wataru Noguchi

Proceedings of the Second IASTED International Conference on Computational Intelligence, 2006

2005

Tolerance on Geometrical Operation as an Attack to Watermarked JPEG Image.

[BibT_eX]

[DOI]

Hiroshi Yamashita

Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2005

A new N-parallel updating method of the Hopfield-type neural network for N-queens problem.

[BibT_eX]

[DOI]

Thanh-Nhat Le

Proceedings of the IEEE International Joint Conference on Neural Networks, 2005

2001

A novel synapses circuit and its application to a neural-based A/D converter.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1995

Associative Dynamics of Competitive Cellular Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Pulse coded cellular neural network and it's hardware implementation.

[BibT_eX]

[DOI]

Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

1994

Bifurcation and Chaos in CMOS Inverters Ring Oscillator.

[BibT_eX]

[DOI]