Cong-Kha Pham
Orcid: 0000-0001-5255-4919
According to our database1,
Cong-Kha Pham
authored at least 129 papers
between 1993 and 2024.
Collaborative distances:
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Bibliography
2024
IEEE Trans. Circuits Syst. II Express Briefs, July, 2024
Compact and Low-Latency FPGA-Based Number Theoretic Transform Architecture for CRYSTALS Kyber Postquantum Cryptography Scheme.
Inf., July, 2024
Realization of Authenticated One-Pass Key Establishment on RISC-V Micro-Controller for IoT Applications.
Future Internet, May, 2024
IEEE Trans. Very Large Scale Integr. Syst., March, 2024
IEEE Access, 2024
IEEE Access, 2024
Construction of Robust Lightweight S-Boxes Using Enhanced Logistic and Enhanced Sine Maps.
IEEE Access, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Unified-pipelined NTT Architecture for Polynomial Multiplication in Lattice-based Cryptosystems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding.
Proceedings of the Computational Science and Its Applications - ICCSA 2024 Workshops, 2024
2023
Transition Factors of Power Consumption Models for CPA Attacks on Cryptographic RISC-V SoC.
IEEE Trans. Computers, September, 2023
A High-Efficiency Modular Multiplication Digital Signal Processing for Lattice-Based Post-Quantum Cryptography.
Cryptogr., September, 2023
Internet Things, July, 2023
On the performance of non-profiled side channel attacks based on deep learning techniques.
IET Inf. Secur., May, 2023
Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA.
Future Internet, May, 2023
A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment.
Comput. Electr. Eng., January, 2023
Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process.
Sensors, 2023
IEEE Access, 2023
FPGA-Based Secured and Efficient Lightweight IoT Edge Devices with Customized RISC-V.
Proceedings of the International Conference on Computing and Communication Technologies, 2023
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
2022
Systems on a Chip With 8 and 32 Bits Processors in 0.18-μm Technology for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Future Internet, 2022
ChaCha20-Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3.
Cryptogr., 2022
IEEE Access, 2022
Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling.
IEEE Access, 2022
Low Complexity Correlation Power Analysis by Combining Power Trace Biasing and Correlation Distribution Techniques.
IEEE Access, 2022
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the International Conference on IC Design and Technology, 2022
Proceedings of the International Conference on IC Design and Technology, 2022
A Combined Blinding-Shuffling Online Template Attacks Countermeasure Based on Randomized Domain Montgomery Multiplication.
Proceedings of the IEEE International Conference on Consumer Electronics, 2022
2021
A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Convergence of 5G Technologies, Artificial Intelligence and Cybersecurity of Networked Societies for the Cities of Tomorrow.
Mob. Networks Appl., 2021
A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction.
IEICE Electron. Express, 2021
A proposal for enhancing training speed in deep learning models based on memory activity survey.
IEICE Electron. Express, 2021
A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse.
IEEE Access, 2021
A Real-Time Cache Side-Channel Attack Detection System on RISC-V Out-of-Order Processor.
IEEE Access, 2021
Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure.
IEEE Access, 2021
Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks.
IEEE Access, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
2020
A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS.
Microprocess. Microsystems, 2020
Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Errors in Stationary Blocks.
EAI Endorsed Trans. Ind. Networks Intell. Syst., 2020
Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB).
IEICE Electron. Express, 2020
IEEE Access, 2020
Proceedings of the 2020 RIVF International Conference on Computing and Communication Technologies, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the ICIIT 2020: 5th International Conference on Intelligent Information Technology, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 1.2-V 162.9 pJ/cycle bitmap index creation core with 0.31-pW/bit standby power on 65-nm SOTB.
Microprocess. Microsystems, 2019
A 1.05-V 62-MHz with 0.12-nW standby power SOTB-65 nm chip of 32-point DCT based on adaptive CORDIC.
IEICE Electron. Express, 2019
A 1.2-V 90-MHz Bitmap Index Creation Accelerator with 0.27-nW Standby Power on 65-nm Silicon-On-Thin-Box (SOTB) CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Live Demonstration: Real-Time Auto-Exposure Histogram Equalization Video-System using Frequent Items Counter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 0.75-V 32-MHz 181-µW SOTB-65nm Floating-point Twiddle Factor Using Adaptive CORDIC.
Proceedings of the IEEE International Conference on Industrial Technology, 2019
Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEICE Electron. Express, 2018
Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC.
IEICE Electron. Express, 2018
IEEE Access, 2018
VLSI Design of Frequent Items Counting Using Binary Decoders Applied to 8-bit per Item Case-study.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
VLSI Design of Floating-Point Twiddle Factor Using Adaptive CORDIC on Various Iteration Limitations.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Hardware Implementation of Background Calibration Technique for TIADCs with Signals in Any Nyquist Bands.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications.
Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 17th International Symposium on Communications and Information Technologies, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
IEICE Electron. Express, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A high-throughput and low-power design for bitmap indexing on 65-nm SOTB CMOS process.
Proceedings of the International Conference on IC Design and Technology, 2016
2015
A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode.
IEICE Trans. Electron., 2015
IEICE Electron. Express, 2015
Design of co-processor for real-time HMM-based text-to-speech on hardware system applied to Vietnamese.
IEICE Electron. Express, 2015
Parallel pipelining configurable multi-port memory controller for multimedia applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the Seventh International Conference on Ubiquitous and Future Networks, 2015
Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEICE Trans. Electron., 2014
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014
2013
Design a Fast CAM-Based Exact Pattern Matching System on FPGA and 0.18µm CMOS Process.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Low Complexity Logarithmic and Anti-Logarithmic Converters for Hybrid Number System Processors and DSP Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of 2013 International Conference on IC Design & Technology, 2013
2012
An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
An Improved Hybrid LUT-Based Architecture for Low-Error and Efficient Fixed-Width Squarer.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Efficient LUT-Based Truncated Multiplier and Its Application in RGB to YCbCr Color Space Conversion.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
2011
An Improved Linear Difference Method with High ROM Compression Ratio in Direct Digital Frequency Synthesizer.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
IEICE Trans. Electron., 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2007
Compensated circuit for Low Dropout Regulator having stable load regulation after consideration of bonding wire resistance.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
An Edge Extraction Method for Color Image Using Multiple-Valued LoG Filter and Color Space.
Proceedings of the 6th Annual IEEE/ACIS International Conference on Computer and Information Science (ICIS 2007), 2007
CMOS Schmitt Trigger Circuit with Controllable Hysteresis Using Logical Threshold Voltage Control Circuit.
Proceedings of the 6th Annual IEEE/ACIS International Conference on Computer and Information Science (ICIS 2007), 2007
2006
A Proposal to Solve N-Queens Problems Using Maximum Neuron Model with A Modified Hill-Climbing Term.
Proceedings of the International Joint Conference on Neural Networks, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
A hardware accelerator for solving the n-queen problem.
Proceedings of the Second IASTED International Conference on Computational Intelligence, 2006
2005
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2005
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995
1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1993
CMOS digital retina chip with multi-bit neurons for image coding.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993