Côme Rozon

According to our database1, Côme Rozon authored at least 20 papers between 1991 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2013
Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs.
J. Electr. Comput. Eng., 2013

2012
Ultra low leakage structures for logic circuits using symmetric and asymmetric FinFETs.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011
A CNFET-based characterization framework for digital circuits.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2008
UDSM subthreshold leakage model for NMOS transistor stacks.
Microelectron. J., 2008

2006
Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries.
Integr., 2006

Accurate Total Static Leakage Current Estimation in Transistor Stacks.
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006

2005
Leakage power dissipation in UDSM logic gates.
Proceedings of the Third IASTED International Conference on Circuits, 2005

2003
IC Bridge Fault Modeling for IP Blocks Using Neural Network-Based VHDL Saboteurs.
IEEE Trans. Computers, 2003

2002
Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models.
Integr., 2002

2001
Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Accurate CMOS Bridge Fault Modeling with Neural Network-Based VHDL Saboteurs.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000
Comprehensive defect analysis and testability of current-mode logic circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Comparing defect coverage for current-mode logic and CMOS VLSI cells.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1998
Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

VHDL Modelling and Analysis of Fault Secure Systems.
Proceedings of the 1998 Design, 1998

1996
On the Use of VHDL as a Multi-Valued Logic Simulator.
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

1995
Improved VLSI Design for Decoding Concatenated Codes Comprising an Irreducible Cyclic Code and a Reed-Solomon Code.
Proceedings of the Information Theory and Applications II, 1995

1994
Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits.
VLSI Design, 1994

1992
Testability analysis and fault modeling of BiCMOS circuits.
J. Electron. Test., 1992

1991
Testability Analysis of CMOS Temary Circuits.
Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991


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