Colin Yu Lin

According to our database, Colin Yu Lin authored at least 18 papers between 2008 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2021

Sparse Tucker Tensor Decomposition on a Hybrid FPGA-CPU Platform.

Weiyun Jiang, Kaiqi Zhang, Colin Yu Lin, Feng Xing, Zheng Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2016

A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability.

Rui Jia, Hai-Gang Yang, Colin Yu Lin, Rui Chen, Xin-Gang Wang, Zhenhong Guo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels.

Colin Yu Lin, Zhenghong Jiang, Cheng Fu, Hayden Kwok-Hay So, Haigang Yang

SIGARCH Comput. Archit. News, 2016

2015

A technology mapper for depth-constrained FPGA logic cells.

Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014

Size aware placement for island style FPGAs.

Junying Huang, Colin Yu Lin, Yang Liu, Zhihua Li, Haigang Yang

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

A semi-supervised modeling approach for performance characterization of FPGA architectures.

Liqun Yang, Haigang Yang, Wei Li, Zhihua Li, Zhihong Huang, Colin Yu Lin

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Exploring architecture parameters for dual-output LUT based FPGAs.

Zhenghong Jiang, Colin Yu Lin, Liqun Yang, Fei Wang, Haigang Yang

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A survey of open source processors for FPGAs.

Rui Jia, Colin Yu Lin, Zhenhong Guo, Rui Chen, Fei Wang, Tongqiang Gao, Haigang Yang

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013

Design space exploration for sparse matrix-matrix multiplication on FPGAs.

Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So

Int. J. Circuit Theory Appl., 2013

Timing-constrained minimum area/power FPGA memory mapping.

Fangqing Du, Colin Yu Lin, Xiuhai Cui, Jiabin Sun, Feng Liu, Fei Liu, Haigang Yang

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency.

Cheng Liu, Colin Yu Lin, Hayden Kwok-Hay So

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012

Energy-efficient dataflow computations on FPGAs using application-specific coarse-grain architecture synthesis.

Colin Yu Lin, Hayden Kwok-Hay So

SIGARCH Comput. Archit. News, 2012

Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs (abstract only).

Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011

A Model for Matrix Multiplication Performance on FPGAs.

Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

A Model for Peak Matrix Performance on FPGAs.

Colin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong

Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

2010

Design space exploration for sparse matrix-matrix multiplication on FPGAs.

Colin Yu Lin, Zheng Zhang, Ngai Wong, Hayden Kwok-Hay So

Proceedings of the International Conference on Field-Programmable Technology, 2010

2009

Operation scheduling for FPGA-based reconfigurable computers.

Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008

A Network Based Functional Verification Method of IEEE 1394a PHY Core.

Colin Yu Lin, Song Cao, Junshe An, Fei Han, Qifei Fan

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008