Clayton B. McDonald

According to our database, Clayton B. McDonald authored at least 6 papers between 1999 and 2015.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2015

Efficient Transistor-Level Symbolic Timing Simulation Using Cached Partial Circuit States.

Clayton B. McDonald, Hsinwei Chou, Vijay Durairaj, Pey-Chang Kent Lin

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2001

CMOS circuit verification with symbolic switch-level timingsimulation.

Clayton B. McDonald, Randal E. Bryant

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models of Custom Macrocells.

Clayton B. McDonald, Randal E. Bryant

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis.

Clayton B. McDonald, Randal E. Bryant

Proceedings of the 38th Design Automation Conference, 2001

2000

Symbolic timing simulation using cluster scheduling.

Clayton B. McDonald, Randal E. Bryant

Proceedings of the 37th Conference on Design Automation, 2000

1999

Symbolic functional and timing verification of transistor-level circuits.

Clayton B. McDonald, Randal E. Bryant

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999