Claudio Passerone

According to our database1, Claudio Passerone authored at least 41 papers between 1995 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
Wino Vidi Vici: Conquering Numerical Instability of 8-bit Winograd Convolution for Accurate Inference Acceleration on Edge.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024

MATAR: Multi-Quantization-Aware Training for Accurate and Fast Hardware Retargeting.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Pruning as a Binarization Technique.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2024

2023
WinoTrain: Winograd-Aware Training for Accurate Full 8-bit Convolution Acceleration.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Accelerating and pruning CNNs for semantic segmentation on FPGA.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2014
3DV - An embedded, dense stereovision-based depth mapping system.
Proceedings of the 2014 IEEE Intelligent Vehicles Symposium Proceedings, 2014

2011
Design of a University Nano-Satellite: the PiCPoT Case.
IEEE Trans. Aerosp. Electron. Syst., 2011

2009
Design of Embedded Systems.
Proceedings of the Embedded Systems Design and Verification, 2009

2007
Architecture of a Small Low-Cost Satellite.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006
Real time operating system modeling in a system level design environment.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Quasi-Static Scheduling of Concurrent Specifications.
Proceedings of the Embedded Systems Handbook., 2005

Design of Embedded Systems.
Proceedings of the Embedded Systems Handbook., 2005

Implementation of a UMTS turbo decoder on a dynamically reconfigurable platform.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Quasi-static scheduling of independent tasks for reactive systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Software Development for High-Performance, Reconfigurable, Embedded Multimedia Systems.
IEEE Des. Test Comput., 2005

A Time Slice Based Scheduler Model for System Level Design.
Proceedings of the 2005 Design, 2005

Design of Embedded Systems.
Proceedings of the Industrial Information Technology Handbook, 2005

2004
An Automated Methodology for Low Electro-Magnetic Emissions Digital Circuits Design.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform.
Proceedings of the 2004 Design, 2004

2003
Metropolis: An Integrated Electronic System Design Environment.
Computer, 2003

A Reconfigurable Processor Architecture and Software Development Environment for Embedded Systems.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Hardware/Software Design Space Exploration for a Reconfigurable Processor.
Proceedings of the 2003 Design, 2003

2002
A Symbolic Approach for the Combined Solution of Scheduling and Allocation.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Designing low electro magnetic emissions circuits through clock skew optimization.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis.
Proceedings of the Embedded Software, Second International Conference, 2002

False Path Elimination in Quasi-Static Scheduling.
Proceedings of the 2002 Design, 2002

Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

Quasi-Static Scheduling of Independent Tasksfor Reactive Systems.
Proceedings of the Applications and Theory of Petri Nets 2002, 2002

Modeling and Designing Heterogeneous Systems.
Proceedings of the Concurrency and Hardware Design, Advances in Petri Nets, 2002

2001
Generation of minimal size code for scheduling graphs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

A software development tool chain for a reconfigurable processor.
Proceedings of the 2001 International Conference on Compilers, 2001

2000
A Case Study in Embedded Systems Design: An Engine Control Unit.
Des. Autom. Embed. Syst., 2000

Task generation and compile-time scheduling for mixed data-control embedded software.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Computing Timed Transition Relations for Sequential Cycle-Based Simulation.
Proceedings of the 1999 Design, 1999

Designing digital video systems: modeling and scheduling.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
Modeling reactive systems in Java.
ACM Trans. Design Autom. Electr. Syst., 1998

A Case Study in Embedded System Design: An Engine Control Unit.
Proceedings of the 35th Conference on Design Automation, 1998

Modeling reactive systems in Java.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

1997
Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis.
Proceedings of the 34st Conference on Design Automation, 1997

Trade-off evaluation in embedded system design via co-simulation.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1995
Using a massively parallel architecture for integrated circuits testing.
Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), 1995


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