Claudio Asero

According to our database1, Claudio Asero authored at least 2 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2024
A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2016
2.4 A 2-to-16GHz BiCMOS ΔΣ fractional-N PLL synthesizer with integrated VCOs and frequency doubler for wireless backhaul applications.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016


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